Polling to determine optimal impedance

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C326S082000

Reexamination Certificate

active

06331785

ABSTRACT:

TECHNICAL FIELD
This embodiments described in this document relate to provision of a generalized interface for signals to be carried on selected communication carriers, and compensation, manually or otherwise, for different impedance levels associated with each of these signal carriers.
BACKGROUND
Many network users regularly transmit and/or receive messages over T
1
carriers in the U.S. and Canada (1.544 Mbits/sec rate; required line impedance of 100 Ohms), over E
1
carriers in Europe (2.048 Mbits/sec rate; required impedances of 75 Ohms or 120 Ohms), and over J
1
carriers in Japan (1.544 Mbits/sec rate; required impedance of 100 Ohms). Presently, transmission and receipt of digital signals on a T
1
line and on an E
1
carrier, for example, require use of separate chips to compensate for different required impedances, different framing patterns, different bit rates and such. In the future, Digital Subscriber Lines (DSLs) will transmit digital signals at selected rates, such as Tn and En and Jn rates (n=1, 1C, 2, 3, 4, 4M . . . ), and will become important for heavy duty information transfer, such as multicast communication for various Internet Protocol (“IP”) applications (voice band telephone, picturephone, combined voice-over-data transfer, video-on-demand, etc.).
SUMMARY
Embodiments described below provide for transmission and/or reception of signals over Tn and En and Jn signal carriers will also require matching of corresponding, and different, impedances for use of these signal carriers. The embodiments further provide for an interface system that determines and provides an optimal input and output impedance required or desired to properly match the network communication carrier. Preferably, for a given impedance value, the interface provides an impedance match whether the signal for transmission or reception is conventional or arises from line reflections produced downstream and received at an input or output terminal of the interface. The system provides an optimal input or output impedance or a chosen impedance for a given signal line. The described embodiments provide a signal amplifier system and interface having a mechanism for testing for and selecting an optimal input impedance and output impedance (referred to collectively herein as a “selected impedance”), depending upon the requirements of the line that will receive and propagate the outgoing signal. One such range is 75-120 ohms, which covers particular T
1
, E
1
, and J
1
carrier line impedances. This range can be extended to cover desired or required impedances that lie outside this range, if desired. In one embodiment, the signal amplifier system uses a differential amplifier with feedback conductances chosen to match the target line impedance for signal transmission. Another embodiment enhances the ability of the signal amplifier system to compensate for signals received from unanticipated signal sources, such as line reflections.
Described in this specification are signal transmit/receive systems that test for and provide correct selected impedances for signals transmitted by the system on a selected signal carrier. In one embodiment, the system includes a signal interface circuit, with at least one signal input terminal and at least one signal output terminal, that has at least one adjustable circuit parameter that can be used to vary an equivalent selected impedance for the interface circuit. The system also includes an impedance adjustment mechanism, connected to the interface circuit, that provides and implements a choice between two or more values for the at least one adjustable circuit parameter that varies the selected impedance for the interface circuit.
The system includes an impedance testing sub-system that tests the signal carrier chosen or used, determines the optimal present impedance for that line, and adjusts one or more circuit parameters to provide this optimal selected impedance. The system, in another embodiment, allows choice of one or more default impedance parameters as an alternative to use of an optimal value for one or more parameters.


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“110-GB/s Simultaneous Bidirectional Transceiver Logic Synchronized with a System Clock,” Toshio Takahaski, et al., IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999 (8 pages).

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