Abrading – Precision device or process - or with condition responsive... – With indicating
Reexamination Certificate
2001-04-13
2004-02-24
Morgan, Eileen P. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
With indicating
C451S010000, C451S011000, C451S041000, C451S287000
Reexamination Certificate
active
06695682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for flatly polishing a plated film and an insulating film formed on a surface of a wafer, for example.
2. Description of the Related Art
Along with higher integration and further down-sizing of semiconductor devices, contraction of wire diameter and wiring pitch as well as multiplication of wiring layer have been promoted to intensify importance of multiple-layer wiring technology in the semiconductor manufacturing process.
Conventionally, aluminum has mainly been used for composing multiple-layer wiring of semiconductor devices. On the other hand, in order to suppress delayed transmission of signal, in the modern design rule dealing with a maximum of 0.18 &mgr;m rule, such a wiring process by way of replacing aluminum with copper has been developed in recent years. Utilization of copper for wiring provides bilateral advantage in terms of low electric resistance and high resistance against electromigration.
In such a process for applying copper to the wiring for example, initially, metal is embedded in slit-form wiring pattern formed in an inter-layer insulating film, and then wiring is formed by removing excessive metal film via a chemical mechanical polishing (CMP) method. Recently, such a wiring process called “damascene” process has become influential. According to the “damascene” process, an etching process of wiring is not required. And yet, since the upper inter-layer insulating film is leveled off naturally, the “damascene” process advantageously simplifies processing steps.
Further, when introducing “dual damascene” process which initially forms wiring slit and contact holes through the inter-layer insulating film at the same time and then embeds both of them with metal, it is possible to drastically save the steps of the wiring processes.
Referring now to the accompanying drawings, a process for forming wiring by applying the above “dual damascene” process is exemplified below. Note that the wiring is formed with copper in this example.
Initially, as shown in
FIG. 39A
, an inter-layer insulating film
2
made of silicon oxide is formed on a silicon semiconductor substrate
1
having properly formed impurities-diffused domain (not shown) therein via a low-pressure chemical vapor deposition (CVD) process, for example.
Next, as shown in
FIG. 39B
, by applying the known photolithographic technique and etching process, a contact hole CH linked with the impurities-diffused region of the semiconductor substrate
1
and slit M for accommodating wiring of a predetermined pattern electrically linked with the impurities-diffused region of the same semiconductor substrate
1
are respectively formed.
Next, as shown in
FIG. 39C
, a barrier film
4
formed on the surface of the inter-layer insulating film
2
, and yet, the same barrier film
4
is also formed through the contact hole CH and inside of the slit M. The barrier film
4
is formed with tantalum Ta, Titanium Ti, TaN, and TiN by applying a known sputtering process. When copper is used for composing wiring and silicon oxide for composing an inter-layer insulating film
2
, since copper significantly diffuses into silicon with a substantial diffusion coefficient, copper is easily oxidized. To prevent copper from being oxidized, the barrier film
4
is necessarily formed.
Next, as shown in
FIG. 39D
, a seed film
5
is formed on the barrier film
4
by way of depositing copper on the barrier film
4
by applying a known sputtering process.
Next, as shown in
FIG. 39E
, in order to fully embed the contact hole CH and the slit M with copper, a copper film
6
is formed by applying a plating process, or a chemical vapor deposition (CVD) process, or a sputtering process, for example.
Next, as shown in
FIG. 39F
, excessive portion of the copper film
6
and the barrier film
4
is removed via a chemical mechanical polishing (CMP) process to level off the copper film
6
.
By implementing the above serial processes, a copper wiring
7
and a contact
8
are eventually formed. By way of repeatedly implementing the above serial processes on the copper wiring
7
, multiple-layer wiring is formed.
When implementing the above-described polishing process, a surface-leveling polishing apparatus is utilized.
FIG. 40
presents a schematic perspective view of a conventional surface-leveling polishing apparatus. The conventional surface-leveling polishing apparatus
20
comprises the following: a rotatable disc-form stationary base
22
adhered with a polishing cloth
21
on the upper surface; a rotatable and vertically movable (in the Z direction) disc-form mounting plate
23
for holding a wafer
10
at the bottom surface; and a nozzle
24
for feeding polishing solution P onto the polishing cloth
21
.
When operating the above-referred conventional surface-leveling polishing apparatus shown in
FIG. 40
, initially, a front surface of the wafer
10
provided with the copper film
6
requiring formation of multi-layer wiring pattern is set prone, and then, the back surface of the wafer
10
is adhered to the bottom surface of the mounting plate
23
or absorbed onto the bottom surface via vacuum pressure.
Next, while jointly rotating the stationary base
22
and the mounting plate
23
, polishing solution P is poured onto the polishing cloth
21
via the nozzle
24
.
Next, by lowering the mounting plate
23
, the front surface of the wafer
10
is pressed against the polishing cloth
21
to polish the copper film
6
requiring formation of the multiple-layer wiring pattern thereon.
Nevertheless, the above conventional surface-leveling polishing apparatus
20
still has a technical problem to solve because polishing amount of the copper film
6
requiring formation of multi-layer wiring pattern thereon still remains unstable inasmuch as the polishing operation is subject to time-control whereby failing to correctly determine actually polished amount until terminating the polishing operation.
Further, polishing precision is variable by actual condition of the polishing cloth
21
whereby unstableness constantly remains in the polishing operation. To secure polishing precision, in many cases, polishing precision is dependent on skill and perception of well-experienced operators.
In addition, because of difference in the removal effect between the inter-layer insulating film
2
, the copper film
6
, and the barrier film
4
, various technical problems such as dishing, erosion (thinning), or recess are apt to be generated.
As shown in
FIG. 41A
, the above-referred dishing designates such a phenomenon in which, if such a wiring
7
having about 100 &mgr;m of width is present in the design rule for ruling a maximum of 0.18 &mgr;m of width, for example, a center portion of the wiring
7
is excessively removed to generate a recessed portion therein. Once the dishing phenomenon is ever generated, because of shortage of sectional area of the wiring
7
, it will cause the wiring
7
to generate an improper electrical resistance value. The dishing phenomenon is apt to be generated when relatively soft copper or aluminum is used for composing the wiring.
On the other hand, as shown in
FIG. 41B
, the above-referred erosion designates such a phenomenon in which a specific portion provided with a very high pattern density containing wiring having 1.0 &mgr;m of width at 50% density within 3000 &mgr;m of range is excessively removed. Once erosion ever takes place, because of short sectional area of the wiring, it will also cause the wiring to generate an improper electrical resistance value.
Further, as shown in
FIG. 41C
, the above-referred recess designates such a phenomenon in which stepwise difference is generated as a result of the lowered wiring
7
at the interface between the inter-layer insulating film
2
and the wiring
7
. Like the above cases, because of short sectional area of the wiring
7
, the wiring
7
will generate an improper electrical resistance value.
On the other hand, when applying the above-referred “damascene”
Sato Shuzo
Suzuki Takashi
Kananen Ronald P.
Morgan Eileen P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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