Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-05-13
2008-05-13
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000, C326S028000, C326S031000
Reexamination Certificate
active
07372293
ABSTRACT:
Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.
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Cox Christopher
Fahmy Hany
Oie Hideo
Vergis George
Cho James
Crawford Jason
Intel Corporation
Pedigo Philip A.
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