Pointer circuit with low surface requirement high speed and low

Details Pointer circuit with low surface requirement high speed and low Pointer circuit with low surface requirement high speed and low

1998-09-25

2000-08-01

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36518905, G11C 700

Patent

active

060976616

ABSTRACT:
In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

REFERENCES:
patent: 5691945 (1997-11-01), Liou et al.
Neil H.E. Weste et al, Principles of CMOS VLSI Design, A Systems Perspective, Addison-Wesley Publishing Company, 1993, Second Edition, Chapter 8, pp. 560-579.
U. Tietze et al, Halbleiter-Schaltungstechnik, Springer-Verlag 9, Auflage, 1990, pp. 572-576.

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