Pointer adjustment jitter cancellation processor utilizing phase

Details Pointer adjustment jitter cancellation processor utilizing phase Pointer adjustment jitter cancellation processor utilizing phase

1996-01-11

1998-08-18

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370516, H04L 700, H04L 2536, H04L 2540

Patent

active

057967962

ABSTRACT:
A system for canceling network pointer adjustment jitters (PAJs). The system is equipped with an elastic buffer to receive, according to a write clock signal, and for temporarily storing a plurality of data bits in the buffer and a pointer interpreter for determining a pointer adjustment event (PAE) and a polarity of bit-stuffing from the data bits. The jitter-cancellation system includes a leaking rate control signal generator for generating a leaking rate control based on the PAE and a polarity signal based on the polarity of bit stuffing. The jitter-cancellation system further includes a phase hopping control device for applying the write clock signal, the leaking rate control signal and the polarity signal for performing a phase-hopping read clock adjustment to generate a read clock signal for controlling a bit-leaking from the elastic buffer such that the bit-leaking is controlled to release in a fraction of a phase step, i. e., a phase of (2.pi.
) for each bit of the data.

REFERENCES:
patent: 5052025 (1991-09-01), Duff et al.
patent: 5268935 (1993-12-01), Mediavilla et al.
patent: 5337334 (1994-08-01), Molloy
Sari, Hikmet, et al., "Cancelation of Pointer Adjustment Jitter in SDH Networks" IEEE Transactions on Communications, vol. 42, No. 12, Dec., 1994 .

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