Patent
1981-01-28
1984-12-18
Clawson, Jr., Joseph E.
357 30, 357 51, 357 59, 357 86, 357 23, H01L 2974
Patent
active
044893400
ABSTRACT:
A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the second P type diffused region and the second N type diffused region, a second gate electrode formed on the second gate insulating layer at a portion above the first gate electrode, a cathode electrode connected to the first N type diffused region, an anode electrode connected to the first P type diffused region and the second gate electrode and a high resistance region formed immediately beneath the first gate insulating layer and between the first and second N type diffused regions.
REFERENCES:
patent: 4224634 (1980-09-01), Suedberg
patent: 4244000 (1981-01-01), Ueda et al.
Hagimura Kazuo
Kato Kotaro
Mori Haruo
Tsukada Hirokazu
Ueda Jun
Clawson Jr. Joseph E.
Nippon Telegraph & Telephone Public Corporation
OKI Electric Industry Co., Ltd.
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