PMOS depletable drain extension made from NMOS dual...

Details PMOS depletable drain extension made from NMOS dual... PMOS depletable drain extension made from NMOS dual...

2006-02-24

2009-06-16

Wojciechowicz, Edward (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S199000, C438S232000, C438S275000, C257S371000, C257S408000

Reexamination Certificate

active

07547592

ABSTRACT:
In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.

REFERENCES:
patent: 4823173 (1989-04-01), Beasom
patent: 5264719 (1993-11-01), Beasom
patent: 5338960 (1994-08-01), Beasom
patent: 6894349 (2005-05-01), Beasom
patent: 6974753 (2005-12-01), Beasom

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