Static information storage and retrieval – Hardware for storage elements
Reexamination Certificate
1999-12-29
2002-04-02
Phan, Trong (Department: 2818)
Static information storage and retrieval
Hardware for storage elements
C365S226000
Reexamination Certificate
active
06366487
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuit devices and more particularly to a semiconductor package that encapsulates at least two integrated circuit chips therein.
BACKGROUND OF THE INVENTION
There have been increasing needs for electrically programmable and erasable semiconductor memory devices that do not require refresh. Particularly, semiconductor memory devices, capable of storing a large amount of data, and capable of rewriting the stored data, has been developed. For example, a NAND-structured flash memory device has been proposed wherein a plurality of memory cells (EEPROM cells) are connected serially. Such a NAND-structured flash memory device is illustrated in cross-section and schematically by FIGS. 11.58 and 11.59 from a handbook by B. Price et al., entitled Semiconductor Memories, John Wiley & Sons Ltd., pp.603-604 (1991).
The NAND-structured flash memory device, however, has a drawback in that it is difficult to perform high-speed read operations because of its cell structure. But, the memory device has the advantages of less power consumption and good program/erase cycling endurance characteristics. Therefore, the NAND-structured flash memory device has been employed as a data storage medium, for example, a CD voice/audio recorder, a digital still camera, and a memory card used in a portable computer.
To meet ever increasing needs for such flash memory applications, a tighter design layout rule is required. Also, packaging of multiple semiconductor integrated circuit memory devices (chips or dies) of the same type in a single semiconductor package has been proposed so that the capacity of a NAND-structured flash memory device can be increased. One of such semiconductor packages is a dual-chip package (DCP).
Referring to
FIG. 1
, a conventional dual-chip package
100
has multiple pins, for example, nREx (read enable), nWEx (write enable), nCEx (chip enable), CLEx (command latch enable), ALEx (address latch enable), and data input/output IO
0
~IO
7
. Package
100
contains two semiconductor integrated circuit chips
110
and
120
, which are encapsulated within the typically lidded and hermetically sealed dual-chip package
100
. Each of the chips
110
and
120
has pads (or bonding pads) arranged so as to correspond to the pins of the dual-chip package
100
. As illustrated in
FIG. 1
, the pads of each of the chips
110
and
120
are bonded to corresponding pins of the package
100
. For example, the pin nREx is coupled in common to a corresponding pad of each of the chips
110
and
120
. Similarly, other pins of the package
100
are coupled in common to corresponding pads of each of the chips
110
and
120
.
FIG. 2
shows the internal architecture of chip
110
embodying a flash memory device. Chip
110
(hereinafter, refer to as the“LSB chip”) comprises a memory cell array
210
, a row decoder (X-DEC) circuit
220
, a page buffer circuit
230
, a column pass gating (Y-Gating) circuit
240
, an I/O buffer circuit
250
, an output driver circuit
260
, a global buffer circuit
270
, a command register
280
, a control logic and high voltage generator
290
, and an X/Y-counter and pre-decoder circuit
300
. As seen from
FIGS. 1 and 2
, pads of chip
110
serve as the ports for address and data input/output as well as command inputs. Chip
120
(hereinafter, referred to as the “MSB chip”) is configured the same as the LSB chip
110
. The operation of chips
110
and
120
is well-known and will not be described herein.
The conventional dual-chip package
100
of
FIG. 1
has twice the capacity of either of the memory chips
110
and
120
encapsulated therein. If each of the chips
110
and
120
is a 64 Mbit-memory device, the capacity of the dual-chip package
100
is 128 Mbit. Therefore, the dual-chip package has a 128 Mbit-pin layout or pinout configuration. Because two memory devices (chips)
110
and
120
are encapsulated in a single package
100
, one of the devices performs its normal operation while the other is idle. If the two devices
110
and
120
were to operate at the same time, proper operation of the dual-chip package
100
cannot be ensured. This is because the input/output pads of the devices
110
and
120
are coupled in common to a single set of input/output pins IO
0
~IO
7
. In other words, to ensure the normal operation of dual-chip package
100
, the chips
110
and
120
encapsulated therein must operate individually. That is, when one of the chips
110
or
120
is selected (or enabled), the other must be unselected (or disabled).
Memory devices
110
and
120
encapsulated in the dual-chip package
100
are distinguishable as the LSB chip and the MSB chip via different addresses (i.e. the devices have a different address coding scheme relative to each other). When the address is provided in common to the memory devices
110
and
120
, one of the memory devices
110
and
120
is selected and the other is not selected. As a result, the LSB and MSB chips
110
and
120
must be manufactured by two different processes so that they operate properly when integrated into a common package.
Typically, when such LSB and MSB chips requiring different address-coding schemes are to be packaged together, different bonding procedures are used so that one of the chips has its pads bonded to a first set of pins on the wafer and the other has its pads bonded to a second set of pins on the wafer. Such special and differential processing during packaging is time consuming and costly.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved package for encapsulating two IC chips, thereby saving time and money.
In order to attain the above objects, according to an aspect of the present invention, there is provided a package having a plurality of pins. The package comprises a first integrated circuit chip having pads corresponding to the pins, and a second integrated circuit chip having pads corresponding to the pins. The first and second integrated circuit chips each have an option pad. And, the first and second integrated circuit chips comprise semiconductor memory devices having the very same address coding schemes, each having an identical memory cell array for storing data; command register for activating one of master signals each indicative of a read mode, program or erase mode in response to an externally applied command; and chip disable circuit coupled to a corresponding option pad. The chip disable circuit including the option pad is provided in accordance with the invention for determining whether or not a corresponding semiconductor memory device is selected. The chip disable circuit resets the command register to disable the activated master signal when the corresponding semiconductor memory device is deselected. The option pad of one of the first and second integrated circuit chips, at a package level, is bonded to a pin supplying a power supply voltage and the option pad of the other thereof, at the package level, is bonded to a pin supplying a ground voltage.
In this embodiment, the chip disable circuit of each of the first and second integrated circuit chips comprises a select signal generator coupled to a corresponding option pad, for generating a chip select signal in response to a voltage signal at the corresponding option pad and to a MSB address signal from outside the chip. The chip select signal indicates whether a corresponding integrated circuit chip is selected or not. A mode reset circuit generates a mode reset pulse signal in response to the chip select signal and the activated master signal so that the command register is reset.
In this embodiment, the semiconductor memory device corresponding to each of the integrated circuit chips further comprises a data input/output buffer circuit which inputs data to be programmed in the memory cell array and outputs data read out from the memory cell array, the data input/output buffer circuit being disabled by a corresponding chip select signal when a corresponding semiconductor memory d
Marger & Johnson & McCollom, P.C.
Phan Trong
Samsung Electronics Co,. Ltd.
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