Plurality of distinct multiplexers that operate as a single mult

Details Plurality of distinct multiplexers that operate as a single mult Plurality of distinct multiplexers that operate as a single mult

1995-09-27

1997-07-08

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326108, 326113, 327408, H03K 19084, H03K 19094

Patent

active

056465580

ABSTRACT:
A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.

REFERENCES:
patent: 4985703 (1991-01-01), Kaneyama
patent: 5162666 (1992-11-01), Tran
patent: 5329180 (1994-07-01), Popli et al.
patent: 5436574 (1995-07-01), Veenstra
patent: 5491431 (1996-02-01), Nasserbakht

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