Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1999-04-29
2002-03-19
Kim, Kenneth S. (Department: 2783)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C341S155000, C713S600000
Reexamination Certificate
active
06360328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a digital signal processor for use in modems (modulator-demodulators) and having a function of changing the sampling frequency, and a power control circuit for reducing wasteful power consumption of an electronic apparatus such as a digital signal processor.
2. Prior Art
There are many modems (modulator-demodulators) which have a function of changing the sampling frequency of a signal transmitted through a communication line, according to the status of the communication line. Therefore, DSPs (digital signal processors) installed in modems of this kind are required to have the function of changing the sampling frequency. Conventional DSPs having such a function of changing the sampling frequency include a DSP which is adapted to change the frequency of a clock for timing control of signal processing according to a designated sampling frequency, and a DSP which stores plural kinds of programs corresponding respectively to a plurality of sampling frequencies and carries out signal processing corresponding to a designated sampling frequency by selecting and executing a corresponding one of the programs.
Of the above conventional DSPs, the former DSP has a complicated circuit configuration for changing the clock frequency, while the latter DSP requires the use of a large capacity memory for storing the plural kinds of programs.
Further, various electronic apparatuses which are currently available, such as DSPs, are provided with power control circuits for reducing wasteful power consumption. Many of such power control circuits are adapted to carry out power down control (power saving control) when a certain condition is satisfied, for example, when no key input operation has been made over a certain time. Various means for power down control are employed, such as cutting off power supply to a specific circuit, and cutting off supply of a clock to a synchronous circuit or reduce the frequency of the clock.
In the above-mentioned prior art power control circuits, power down control is not carried out so long as a key input operation is made. However, even during a time period when the power down control is not carried out, main circuits within the electronic apparatus do not carry out any processing or are in a so-called idle state, while wastefully consuming electric power. This problem is not limited to a case where power down control is carried out on condition that no key input operation is made. For example, there are communication apparatuses which carry out communication using particular slots which are previously allotted, by time shared control. Many communication apparatuses of this kind are adapted to carry out power down control in a time zone other than the particular slots. In such communication apparatuses, circuits within the apparatus do not operate over the entire time period of the particular slots, but even in the particular slots there is a time period when the apparatus is in an idle state. In the conventional power down control technology, however, sufficient saving of power consumption cannot always be achieved since electric power is wastefully consumed in an unrestricted manner during the time period when the electric apparatus is in an idle state.
SUMMARY OF THE INVENTION
It is a first object of the invention to provide a digital signal processor, which has a simple construction but is capable of performing signal processing in a manner corresponding to a plurality of sampling frequencies, using a small-scaled program.
It is a second object of the invention to provide a power control circuit which is capable of reducing wasteful power consumption by circuits which are in the so-called idle state even during a time period when power down control is not carried out in the prior art, thereby achieving sufficient saving of the power consumption.
To attain the first object, according to a first aspect of the invention, there is provided a digital signal processor for performing signal processing corresponding to a designated one of a plurality of sampling frequencies, comprising a slot changing device that carries out changeover of slots at a frequency equivalent to a common multiple of the plurality of sampling frequencies, a slot cycle setting device that sets a slot cycle formed of the slots corresponding in number to a sampling period determined by the designated one of the plurality of sampling frequencies, and an executing device that executes routines corresponding to the slots forming the slot cycle, with a repetition period determined by the set slot cycle, to thereby perform signal processing corresponding to the designated one of the plurality of sampling frequencies in a time-discrete manner.
In a preferred form of the first aspect of the invention, the digital signal processor comprises a timing generating device that generates a slot timing signal indicative of timing of changeover of slots being a time unit of timing control of the signal processing, the slot timing signal having a frequency equivalent to a common multiple of the plurality of sampling frequencies, and an instruction readout clock having a frequency higher than the frequency of the slot timing signal, an instruction memory storing a program comprising groups of instructions for signal processing corresponding to the plurality of sampling frequencies, a) the program comprising a plurality of routines corresponding respectively to a predetermined number of the slots continuously arranged, b) ones of the groups of instructions for signal processing corresponding to each of the plurality of sampling frequencies being distributed in ones of the plurality of routines corresponding respectively to ones of the slots forming a slot cycle starting from a first one of the predetermined number of slots and having a length corresponding to the each of the plurality of sampling frequencies, c) a first readout control instruction being provided for the ones of the groups of instructions for signal processing corresponding to the each of the plurality of sampling frequencies, distributed in the ones of the plurality of routines, for reading out the ones of the groups of instructions for signal processing corresponding to the each of the plurality of sampling frequencies when the each of the plurality of sampling frequencies is designated, d) a second readout control instruction being provided for one of the ones of the plurality of routines corresponding to a last one of the ones of the slots forming the slot cycle, for causing execution of another one of the ones of the plurality of routines corresponding to a first one of the ones of the slots forming the slot cycle, next to execution of the one of the ones of the plurality of routines corresponding to the last one of the ones of the slots forming the slot cycle, when the each of the plurality of sampling frequencies is designated, e) a halt instruction being provided at an end of one of the routines corresponding to each of the ones of the slots forming the slot cycle, for instructing halting of reading-out of at least one corresponding group of the groups of instructions; an operation device that performs operation for signal processing according to instructions read out from the instruction memory, and an instruction readout control device that is responsive to generation of the slot timing signal, for starting reading out one of the routines corresponding to each of the slots from the instruction memory, reading out at least one of the groups of instructions for signal processing contained in the readout one of the routines according to the first readout control instruction, and delivering the readout at least one of the groups of instructions to the operation device, the instruction readout control device being responsive to the halt instruction read out from the instruction memory, for halting reading-out of the groups of instructions until the slot timing signal is again generated, and responsive to the second readout control instruction read out from the ins
Muraki Yasuyuki
Yamamoto Yusuke
Kim Kenneth S.
Morrison & Foerster / LLP
Yamaha Corporation
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