Plural port memory system utilizing a memory having a read port

Details Plural port memory system utilizing a memory having a read port Plural port memory system utilizing a memory having a read port

1993-10-05

1994-12-20

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518903, 36518905, 36523002, 36523005, 36523008, G11C 700, G11C 800

Patent

active

053750896

ABSTRACT:
A plural port memory system utilizing a memory having a write port and a separate read port wherein the write port includes a write data line, a write address, and a write enable line and wherein the read port includes a read data line, a read address, and a read enable line. The plural port memory system includes: a plurality of interfaces for reading from and writing to the memory, each interface having a read request line and a write request line; and a controller coupled to each of the read and write request lines, and the read and write enable lines for arbitrating access to the memory by the plurality of interfaces.

REFERENCES:
patent: 4967398 (1990-10-01), Jamoua et al.
patent: 5036491 (1991-07-01), Yamaguchi
patent: 5276842 (1994-01-01), Sugita

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