Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
1999-04-13
2001-03-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S201000, C365S230030, C714S763000
Reexamination Certificate
active
06198667
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a multi-bank memory array, and more particularly, to an improved semiconductor memory device having a multi-bank memory array and data input/output method thereof, capable of collectively performing writing and reading with regard to a plurality of memory banks when testing a plurality of memory banks.
2. Description of the Background Art
In order to store massive information in a memory, a plurality of memory arrays are connected in parallel inside one semiconductor memory chip so as to effectively employ the memory. Such a memory array is referred to as memory bank. For simplicity of explanation, it is assumed that there are two memory banks in the application of the present invention.
FIG. 1
is a block diagram illustrating a conventional semiconductor memory device having a multi-bank memory array. As shown therein, a command decoder
1
receives a plurality of control signals /CS, /RAS, /CAS, /WE to allow a system to implement various operations. A controller
2
controls respective units in accordance with the command from the command decoder
1
. A mode register
3
stores therein operation characteristic values such as system latency, burst length, etc., while externally receiving address signals A
0
-A
11
so as to be setup.
The address signals A
0
-A
10
among the external address signals A
0
-A
11
are applied to a row address butter
4
and a column address buffer
5
, and the row address buffer
4
transfers a row address signal to two memory banks
6
,
7
, and also the column address buffer
5
transfers a column address signal to the two memory banks
6
,
7
, whereby a data input/output path of the two memory banks
6
,
7
is formed. Meanwhile, the memory banks
6
,
7
respectively include a row decoder, a column decoder and a memory array.
A bank selector
8
is enabled by an enable signal BANKEN from the controller
2
and alters and outputs respective levels of first and second bank enable signals XBANK
1
, XBANK
2
in accordance with the bank selection address signal A
11
.
Among the two memory banks
6
,
7
, the first memory bank
6
is enabled by the first bank enable signal XBANK
1
, and the second memory bank
7
is enabled by the second bank enable signal XBANK
2
. A plurality of internal word lines are enabled by internal addresses outputted from row and column address buffers
4
,
5
, whereby the first and second memory banks
6
,
7
store data or output stored data.
An input controller
9
is enabled by an input enable signal IEN from the controller
2
or an output enable signal OEN and outputs a write and read enable signal to a buffer unit
10
in accordance with the bank selection address signal A
11
.
The buffer unit
10
is controlled by a write enable signal WEN and a read enable signal REN from an input/output controller
9
and transfers data to respective memory arrays of the two memory banks
6
,
7
or externally outputs the data outputted from the respective memory array.
In the thusly constituted conventional apparatus, the two memory banks
6
,
7
are selectively enabled in accordance with a logic state of the bank selection address signal A
11
, and the system mode is divided into a row access mode, a write mode, or a read mode, in accordance with the state of a command signal COMMAND (see FIG.
2
).
With reference to
FIG. 2
, the row access operation will now be described.
FIG. 2
shows timing diagrams illustrating row access, wherein a clock signal CLK, a command signal COMMAND and address signals A
0
-A
11
are respectively shown.
At time point t21, if the command signal COMMAND is activated for row access, a high level enable signal BANKEN is outputted from the controller
2
to the bank selector
8
. Also, when the bank selection address signal A
11
becomes a high level at time point t21, the bank selector
8
outputs a high level first bank enable signal XBANK
1
and a low level second bank enable signal XBANK
2
. Likewise, since the first bank enable signal XBANK
1
becomes a high level, the first memory bank
6
is row-accessed, whereby the first memory bank
6
becomes ready to perform a write or read operation, whereas the second memory bank
7
is not row-accessed.
Also, at time point t21, the address signals A
0
-A
10
are applied in common to the two memory banks
6
,
7
via the row address buffer
4
. At this time, since only the first memory bank
6
is row-accessed as described above, although a word line of the first memory bank
6
is enabled, the word line of the second memory bank
6
is not enabled.
At time point t22 after a time period tRRD has lapsed, when the bank selection address signal A
11
is transited to a low level, the second memory bank
7
becomes low-accessed, whereas the first memory bank
6
is not low-accessed. That is, the logic level of the two bank enable signals XBANK
1
, XBANK
2
of the bank selector
8
becomes contrary to the logic level at time point t21 as discussed above. In other words, when a low level bank selection address signal A
11
is applied, the first bank enable signal XBANK
1
is outputted at a low level and the second bank enable signal XBANK
2
is outputted at a high level. Accordingly, the word line of the first memory bank
6
is not enabled and the word line of the second memory bank
6
is enabled.
Here, the time period tRRD represents a row active-to-active interval so that the one memory bank
6
is enabled and the other memory bank
7
is enabled, and it is determined by an initial design.
The write operation will now be described.
FIG. 3
shows timing diagrams illustrating write operation. As shown therein, when a command signal COMMAND is activated in order to set a memory bank as a write mode at time point t31 and the bank selection address signal A
11
is at high level, the first memory bank
6
becomes enabled. Also, the input/output controller
9
outputs a high level read enable signal REN so that the buffer unit
10
forms a data read path with regard to the first memory bank
6
. Accordingly, the data DQ as shown in
FIG. 3
is transferred to the first memory bank
6
, thereby performing a write operation with regard to the memory bank
6
. Here, symbols DA
0
, DA
1
, DA
2
and DA
3
denote that the data to write is applied to the first memory bank
6
.
Meanwhile, when the bank selection address signal A
11
is at a low level, a data read path with regard to the second memory bank
7
is formed by the input/output controller
9
, whereby the write operation with regard to the second memory bank
6
is implemented.
Referring to
FIG. 4
, a read operation will now be described.
The read operation is implemented in a method similar to the write operation. That is, the command signal COMMAND is activated in order to determine a memory bank as a read mode at time point t41. When the bank selection address signal A
11
becomes a high level, a data write path with regard to the first memory bank
6
is formed by the input/output controller
9
, whereby data DQ as shown in
FIG. 4
is externally outputted via the first output buffer OBUF
1
.
Meanwhile, when the bank selection address signal A
11
is at a low level, the read operation with regard to the second memory bank
6
is implemented.
Banks are individually distinguished in the conventional art because a row access is implemented with regard to one bank. After a predetermined time tRRD, the row access is performed with regard to other banks so as to decrease latency. However, respective banks are separately accessed so as to disadvantageously increase access time. Further, as the number of banks increases so does the access time in proportion thereto.
Moreover, in case of system testing, respective data values used for same cell locations with regard to a plurality of banks are identical in most instances. In that case, as shown in
FIG. 2
, the predetermined time tRRD set for respective access to banks and access time for remaining banks except for one memory bank are unnecess
Hyundai Electronics Industries Co,. Ltd.
Nelms David
Yoha Connie C.
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