Plural bus arbitrations per cycle via higher-frequency arbiter

Details Plural bus arbitrations per cycle via higher-frequency arbiter Plural bus arbitrations per cycle via higher-frequency arbiter

2007-02-06

2007-02-06

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C713S501000, C370S462000

Reexamination Certificate

active

11066507

ABSTRACT:
An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The arbiter may arbitrate for two or more slave devices, or may arbitrate multiple master device requests directed to the same slave device. The arbiter frequency may be variable, and may be predicted based on, e.g., prior bus activity. If only one bus transaction request is pending, the arbiter frequency may equal the bus frequency. The results of an earlier arbitration decision may be utilized to more intelligently make subsequent arbitration decisions in the same bus frequency clock cycle.

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