Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1998-03-12
2000-11-07
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
25049222, G06F 1750, G06F 1710, G21K 510
Patent
active
061451185
ABSTRACT:
The invention provides a plotting pattern data production method suitable for use for production of a mask for exposure or a semiconductor integrated circuit wherein a minimum plotting grid of a magnitude used in an existing apparatus can be used and a semiconductor integrated circuit pattern having a desired size can be formed accurately. The method comprises the steps of: (A) producing an n-fold design pattern by multiplying a design pattern to n times a minimum design pattern unit length (where n>1) and then converting the n-fold design pattern so that profiles thereof may come on those minimum plotting grids adjacent the profiles thereby to obtain a plotting pattern, and (B) (a) setting, for each portion of the plotting pattern which includes any of the profiles of the n-fold design pattern, a dose amount in accordance with a ratio in area of the n-fold design pattern which occupies the minimum plotting grid, but (b) setting a predetermined dose amount for each portion of the plotting pattern which does not include any profile of the n-fold design pattern.
REFERENCES:
patent: 5008553 (1991-04-01), Abe
patent: 5313068 (1994-05-01), Meiri et al.
patent: 5754443 (1998-05-01), Manabe
patent: 5933212 (1999-08-01), Kasuga
Garbowski Leigh Marie
Lintz Paul R.
Sony Corporation
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