PLO device

Details PLO device PLO device

2002-08-05

2004-10-19

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S327000, C375S294000, C375S215000, C398S202000, C398S155000

Reexamination Certificate

active

06807245

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLO (Phase Locked Oscillator) device, and more particularly, to a PLO device for carrying out clock recovery based on an input signal.
2. Description of the Related Art
A PLO is a circuit wherein feedback control is performed for oscillation so that the phase difference between an input signal supplied from outside and the output of an oscillator within the loop becomes constant, to obtain an oscillating output in phase with the input signal. PLOs are used in various fields such as optical communication field, mobile communication field and digital audio field, and the importance thereof is growing in recent years.
FIG. 41
shows the configuration of a conventional PLO circuit. The PLO circuit
8
comprises a discriminator (comparator)
81
, a D-type flip-flop (FF)
82
, an exclusive OR gate (EOR)
83
, a loop filter
84
, and a VCO (Voltage Controlled Oscillator) section
85
.
The connections of the elements will be described first. The output of the discriminator
81
is connected to the D terminal of the FF
82
and one input terminal of the EOR
83
. The Q terminal of the FF
82
is connected to the other terminal of the EOR
83
, the output of which is input to the loop filter
84
. The output of the loop filter
84
is input to the VCO section
85
, whose output is connected to the clock input terminal of the FF
82
.
The discriminator
81
discriminates between “0” and “1” of input signal D
0
. The FF
82
shifts input data D
1
for a time corresponding to half of one time slot, and outputs shifted data D
2
. The EOR
83
detects the phase difference between the two, phase-shifted and unshifted signals, and outputs difference data D
3
. The loop filter
84
removes an alternating-current component from the difference data D
3
and outputs a direct-current control voltage D
4
. The VCO section
85
oscillates at an output frequency (input clock for the FF
82
) proportional to the control voltage D
4
.
FIG. 42
is a time chart illustrating operation of the PLO circuit
8
. The figure shows the waveforms of the input data D
1
, shifted data D
2
, difference data D
3
and control voltage D
4
, which are based on an exemplary sequence pattern of “0s” and “1s”.
The pulse width of the difference data D
3
varies in accordance with a phase difference &phgr; between the input data D
1
and the shifted data D
2
. Specifically, the pulse width decreases with decrease in the phase difference &phgr; and increases with increase in the phase difference &phgr;.
The control voltage D
4
is a direct-current voltage (solid line) (rectangular wave indicated by the dashed line shows the difference data D
3
). If the phase difference &phgr; decreases and the waveform of the shifted data D
2
shifts forward relative to the input data D
1
, then the pulse width of the difference data D
3
narrows, so that the control voltage D
4
approaches zero.
If the phase difference &phgr; increases and the waveform of the shifted data D
2
shifts backward relative to the input data D
1
, the pulse width of the difference data D
3
widens, and thus the control voltage D
4
increases away from zero.
In the PLO circuit
8
, the control voltage D
4
, which is based on the oscillating output, is fed back to the VCO section
85
. Thus, control is performed in a manner such that if the oscillating output is delayed, the oscillation frequency is increased to advance the phase, and that if the oscillating output is advanced, the oscillation frequency is decreased to delay the phase, whereby an oscillation frequency in phase with the input signal can be output.
However, the conventional PLO circuit
8
described above is very often adjusted such that clock recovery is carried out based on the input signal D
0
having an average pattern (e.g. PN (Pseudo-Noise) pattern etc.) of transition rate, and thus a problem arises in that clock phase change or out-of-phase error occurs when the circuit is input with a signal having a pattern of larger or smaller transition rate.
The transition denotes a level change of the input signal D
0
from “0” to “1” or from “1” to “0”, and the transition rate represents the number of level changes per unit time.
FIG. 43
illustrates the relationship between the control voltage D
4
and the phase difference &phgr;. The vertical axis indicates the control voltage D
4
, and the horizontal axis indicates the phase difference &phgr;. The control voltage D
4
(solid line) is derived based on the input signal D
0
, while a control voltage D
4
-
1
(dotted line) is derived based on an input signal (hereinafter referred to as repeating-pattern signal) having a repeating pattern (pattern with large transition rate) in which “0” and “1” are alternately repeated.
In either case, the control voltage becomes zero when the phase difference &phgr; is 0 or n&pgr; (n=±2, ±4, . . . ), and rises linearly within one period (pattern is repeated such that the control voltage rises as the phase difference &phgr; increases within a period and drops to zero at the end of the period).
The repeating-pattern signal has a high frequency of level changes from “0” to “1” or from “1” to “0”, and thus has a larger transition rate than the input signal D
0
. Accordingly, when the repeating-pattern signal is input to the PLO circuit
8
of
FIG. 41
, the difference data generated within the circuit through the phase comparison contains an increased high-frequency component, so that the loop filter
84
outputs the control voltage D
4
-
1
which has a larger value than the control voltage D
4
derived based on the input signal D
0
.
FIG. 44
illustrates how clock phase change and out-of-phase error occur. It is assumed that for the control voltage D
4
derived based on the input signal D
0
, a reference voltage Vref, or a threshold, of the VCO section
85
is set approximately at the middle of the inclined straight line of the control voltage D
4
, and that the reference point is at a position P
1
(where normal locking is achievable).
Also, in the figure, H represents a pull-in range (phase controllable range) of the PLO circuit
8
. If the varying point of the control voltage D
4
is within the pull-in range H, the PLO circuit
8
is capable of normal locking.
On the other hand, if the repeating-pattern signal is input to the PLO circuit
8
and the control voltage D
4
changes to a control voltage D
4
-
1
a
, the reference point shifts from the position P
1
to a position P
2
. In this case, since the reference point is still within the pull-in range H, the phase can be locked but at a position deviated forward, with the result that a clock phase change occurs.
In the case of a control voltage D
4
-
1
b
with an even greater voltage value, the reference point shifts to a position P
3
. In this case, since the reference point is outside the pull-in range H, the phase fails to be locked and an out-of-phase error occurs.
In this manner, in cases where a repeating pattern having a large transition rate is input to the PLO circuit
8
which is designed to be supplied with an average transition rate pattern, the PLO circuit
8
malfunctions. Namely, the control voltage is dependent on the transition rate, and therefore, if the transition rate changes, the conventional circuit fails to perform stable operation.
In the foregoing, malfunction attributable to change in the transition rate is explained on the premise that the control voltage is dependent on the transition rate. In practice, however, the control voltage is dependent not only on the transition rate but on S/N (Signal Noise Ratio). Accordingly, if a PLO circuit designed to operate under high S/N conditions is used in poor S/N conditions, the circuit fails to operate normally and a similar malfunction such as clock phase change or out-of-phase error occurs.
SUMMARY OF THE INVENTION
The present invention was created in view of the above circumstances, and an object thereof is to provide a PLO device in which parameters related to transition rate and S/N are re

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