Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2003-10-08
2008-12-16
Liu, Shuwang (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S371000, C375S373000, C375S374000, C375S376000
Reexamination Certificate
active
07466785
ABSTRACT:
A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).
REFERENCES:
patent: 6853696 (2005-02-01), Moser et al.
patent: 2002/0085657 (2002-07-01), Boerstler
J. Savoj, et. al. Design of Half-Rate Clock and Data Recovery Circuits fro Optical Communication Systems; vol. CONF. 38, Jun. 2001; pp. 121-126 USA.
Chan Geun Yoon et. al.; Digital Logic Implementation of the Quadricorrelators for Frequency Detector; vol. 2 SYMP 37, Aug. 1994; pp. 757-760.
Leenaerts Dominicus Martinus Wilhelmus
Sanduleanu Mihai Adrian Tiberiu
Liu Shuwang
NXP B.V.
Perez James M
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