PLL noise smoothing using dual-modulus interleaving

Details PLL noise smoothing using dual-modulus interleaving PLL noise smoothing using dual-modulus interleaving

2008-09-09

2008-09-09

Tse, Young T. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S160000, C331S00100A

Reexamination Certificate

active

11202387

ABSTRACT:
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.

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