PLL frequency synthesizer with lock detection circuit

Details PLL frequency synthesizer with lock detection circuit PLL frequency synthesizer with lock detection circuit

1998-06-29

2004-06-29

Ghayour, Mohammad H. (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000

Reexamination Certificate

active

06757349

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a locking detection circuit used in a PLL (phase locked loop) frequency synthesizer for detecting whether the PLL is locked.
2. Description of the Related Art
Referring to
FIG. 1
, a conventional PLL frequency synthesizer
10
comprises a reference frequency demultiplier counter
11
, a comparison frequency demultiplier counter
12
, a phase comparator
13
, a charge pump
14
, a low pass filter (hereafter abbreviated as LPF)
15
, a voltage controlled oscillator (hereafter abbreviated as VCO)
16
and a lock detection circuit
17
.
The reference frequency demultiplier counter
11
produces a reference signal fr from a signal of generated by a crystal oscillator
18
through frequency demultiplication. The comparison frequency demultiplier counter
12
produces a compared signal fp obtained from an output signal fv from the VCO
16
through frequency demultiplication. The phase comparator
13
produces a first and a second phase difference signals &phgr;R, &phgr;P in accordance with a phase difference between the reference signal fr and the compared signal fp. On the basis of both phase difference signals &phgr;R, &phgr;P through the operations of the charge pump
14
and the LPF
15
, the magnitude of voltage of a control signal VT which is input to the VCO
16
is changed. The PLL circuit
10
also operates to lock the frequency of the output signal fv from the VCO
16
to a desired frequency.
The lock detection circuit
17
receives the first and second phase difference signals &phgr;R, &phgr;P from the phase comparator
13
, and also receives a reference clock signal CK from the reference frequency demultiplier counter
11
which is obtained by the frequency demultiplication of the signal of from the crystal oscillator
18
at a given ratio. The lock detection circuit
17
, which operates in synchronism with the reference clock signal CK, detects whether the output signal fv is locked on the basis of the first and second phase difference signals &phgr;R, &phgr;P, and generates a locking detection signal LD having a level which depends on the result of such detection.
Referring to
FIG. 2
, there is shown a specific circuit arrangement of the lock detection circuit
17
. As shown, the lock detection circuit
17
includes a NAND circuit
21
that receives the first and the second phase difference signals &phgr;R, &phgr;P from the phase comparator
13
and provides an output signal S
1
corresponding to the phase difference which is represented by each pulse width of the signals &phgr;R, &phgr;P. A data flip-flop circuit (hereafter referred to as FF circuit)
22
has a data terminal D for receiving the output signal S
1
and a clock terminal CK for receiving the reference clock signal CK, and delivers an output signal S
2
corresponding to the output signal S
1
at its output terminal Q in synchronism with the rising edge of the reference clock signal CK.
A NAND circuit
23
receives the signals S
1
, S
2
, and delivers its to an inverter circuit
24
. An inverted signal S
3
is supplied to a data terminal D of an FF circuit
25
from the inverter circuit
24
.
The FF circuit
25
has a clock terminal for receiving the reference clock signal CK, and provides an output signal S
4
at its output terminal Q which depends on the inverted signal S
3
in synchronism with the rising edge of the reference clock signal CK.
An inverter circuit
30
receives the output signal S
4
and generates an inverted signal S
4
a. A synchronous counter is formed by a plurality of FF circuits
27
,
28
,
29
. The first stage FF circuit
27
has a data terminal D, to which the inverted signal S
4
a is applied. Each of the FF circuits
27
to
29
has a clock terminal, to which an inverted signal S
1
a, formed by an inverter circuit
26
with the signal S
1
, is applied. The FF circuit
27
delivers an output signal S
5
at its output terminal Q in synchronism with the rising edge of the inverted signal S
1
a (or the falling edge of the signal S
1
). The FF circuit
28
has a data terminal D, to which the output signal S
5
is applied, and delivers an output signal S
6
at its output terminal Q in synchronism with the falling edge of the output signal S
1
. The FF circuit
29
has a data terminal D, to which the output signal S
6
is applied, and delivers an output signal S
7
at its output terminal Q in synchronism with the falling edge of the output signal S
1
. The output signals S
5
, S
6
, and S
7
are input to a NAND circuit
31
, which then delivers the locking detection signal LD.
In the lock detection circuit
17
, when one or both of the phase difference signals &phgr;R, &phgr;P has an L level, the NAND circuit
21
delivers the signal S
1
which has an H level. The phase difference signals &phgr;R, &phgr;P each have a pulse width which is related to a phase difference between the reference signal fr and the compared signal fp, as will be further described later. Accordingly, the NAND circuit
21
delivers the signal S
1
of the H level for a time interval corresponding to the phase difference between the signals fr, fp. The greater the phase difference between the signals fr, fp, the longer the pulse width of the signal S
1
or vice versa.
The lock detection circuit
17
detects whether the PLL circuit
10
is locked on the basis of the number of rising edges of the reference clock signal CK which are input during a time interval corresponding to the pulse width of the output signal S
1
or a time interval during which the NAND circuit
21
delivers the output signal S
1
having the H level, and delivers the locking detection signal LD having a level which depends on the result of such detection. Thus it will be seen that the lock detection circuit
17
requires the reference clock signal CK of a higher frequency than the frequencies of the reference signal fr and the compared signal fp. Hence, the reference frequency demultiplier counter
11
produces the reference clock signal CK by the frequency demultiplication at a ratio which is less than the ratio of frequency demultiplication applied to the reference signal fr. Alternatively, the reference frequency demultiplier counter
11
may deliver the input crystal oscillator signal of directly as the reference clock signal CK.
The synchronous counter delivers the locking detection signal LD having an H level only when a phase coincidence is reached between the reference signal fr and the compared fp a number of times which is equal to the number of counter stages or more. This prevents the locking detection signal LD having the H level from being delivered from the lock detection circuit
17
for an accidental phase coincidence between the both signals fr, fp.
Digital mobile equipment generally requires the output signal fv of a higher frequency than analog mobile equipment, and consequently, the PLL circuit
10
produces the reference signal fr and the compared signal fp of higher frequencies, which then approach the frequency of the reference clock signal CK. This may result in a malfunctioning of the lock detection circuit
17
.
For example, if the PLL circuit is locked between two consecutive rising edges of the reference clock signal CK, the lock detection circuit
17
may be unable to detect the locked condition, thus undesirably delivering the locking detection signal LD having the L level. Because the locking detection signal LD is used in controlling the charge pump
14
, the LPF
15
or other external circuit, there are adverse influences upon the operation of the entire PLL circuit or external circuit, causing instability in the operation of the mobile equipment.
An object of the present invention is to provide a lock detection circuit and a PLL frequency synthesizer capable of reliably detecting a locked condition.
SUMMARY OF THE INVENTION
To achieve the above objective, the present invention provides a lock detection circuit for detecting whether a phase of a compared signal is locked with that of a reference signal based on first and second phase

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