PLL frequency synthesizer using frequency dividers reset by...

Details PLL frequency synthesizer using frequency dividers reset by... PLL frequency synthesizer using frequency dividers reset by...

1998-05-01

2001-01-09

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S375000, C327S147000, C327S156000, C327S160000

Reexamination Certificate

active

06173025

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to phase-locked loop frequency synthesizers and more specifically, the invention relates to implementation of a PLL frequency synthesizer capable of fast lock-in operation at the instant immediately after frequency dividers are energized to operate a voltage controlled oscillator in a closed-loop mode. The present invention is particularly suitable for power saving PLL frequency synthesizers.
2. Description of the Related Art
Fast lock-in capability is an important feature of a phase-locked loop regardless of its application in order to recover from an out-of-phase condition. Power saving is another important feature of the phase-locked loop if it is used in portable radio receivers. Since power consumption of a PLL frequency synthesizer of a radio receiver accounts for a substantial proportion of its total power, battery supply of its two frequency dividers is periodically interrupted to operate its voltage-controlled oscillator in an open-loop mode. As shown and described in Japanese Laid-Open Patent Specification Sho-60-248022, energy stored in the lowpass (loop) filter during a closed-loop mode is utilized during the next open-loop mode to enable the VCO to produce its output. During the closed-loop mode, the input signals of the phase detector must be resynchronized, or locked in phase to each other even if they are synchronized in frequency. Since longer the time it takes for the closed-loop mode to resynchronize the shorter the time allowed for the open-loop mode to continue, it is desirable from the power savings view point that the two frequency dividers are locked in phase as quickly as possible.
Japanese Laid-Open Patent Specification Sho-64-1330 discloses a fast lock-in power-saving PLL frequency synthesizer whose resynchronization process is controlled by the use of two gate circuits as illustrated in FIG.
1
. One of the gate circuits, indicated at
2
, is connected in the circuit between a quartz oscillator
1
and a divided-by-M frequency divider
3
, the other gate circuit
8
being connected in the circuit between a voltage-controlled oscillator
7
and a divide-by-N frequency divider
9
. The scaling factor M is constant, while the scaling factor N is variable in accordance with an externally supplied frequency (channel) control signal. The phase difference between the outputs of the frequency dividers
3
and
9
is detected by a phase detector
4
and supplied through a switch
5
and a lowpass filter
7
to the VCO
7
. To the outputs of the frequency dividers is connected a control circuit
10
to which power saving pulses are supplied from an external source. Although not shown in
FIG. 1
, power supply to the frequency dividers
3
and
9
is cut off and the switch
5
is turned off to operate the VCO
7
in an open-loop mode. Immediately after the frequency dividers are activated again, but before the switch
5
is turned on to operate the VCO in a closed loop mode, the control circuit
10
determines whether the frequency divider
9
is lagging or leading with respect to the frequency divider
3
. Control circuit
10
turns off the gate circuit
2
if the divider
9
is lagging and turns off the gate circuit
8
if it is advancing. The length of the turn-off time of these gate circuits is determined so that the inputs of the phase detector
4
are aligned in phase with each other.
However, when one of the gate circuits is turned off, there is a possibility of one of the frequency dividers producing at least one error count, and there is also a possibility of another error count when the gate circuit is turned on. In the prior art, there is a likelihood of the occurrence of a maximum initial phase difference of two cycles. Therefore, the prior art approach is still not sufficient for fast lock-in operation because of imprecision timing control of the gate circuits.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a PLL frequency synthesizer capable of fast lock-in operation with precision.
According to a first aspect, the present invention provides a phase-locked loop frequency synthesizer comprising a reference frequency oscillator, a first resettable frequency divider having a fixed scaling factor connected to the reference frequency oscillator, a voltage-controlled oscillator, and a second resettable frequency divider having a variable scaling factor connected to the voltage-controlled oscillator. A phase difference is detected by a phase detector between the first and second frequency dividers and a first output pulse representative of the phase difference is produced when the second frequency divider is leading and a second output pulse representative of the phase difference is produced when the second frequency divider is lagging. A charge integrating circuit integrates the first and second output pulses to supply a phase difference signal to a lowpass filter which filters out high frequency components of the phase difference signal and operates the voltage-controlled oscillator. A control circuit is responsive to the first and second output pulses of the phase detector for detecting an initial phase difference which occurs between the first and second frequency dividers immediately after the instant the first and second frequency dividers are energized and resetting one of the first and second frequency dividers so that the frequency dividers are aligned in phase. A gate circuit is connected between the phase detector and the charge integrating circuit for blocking the passages of the first and second output pulses of the phase detector to the charge integrating circuit when the initial phase difference is detected by the control circuit.
According to a second aspect, the present invention provides a phase-locked loop frequency synthesizer comprising a reference frequency oscillator, a first resettable frequency divider having a fixed scaling factor connected to the reference frequency oscillator, a voltage-controlled oscillator, and a second resettable frequency divider having a variable scaling factor connected to the voltage-controlled oscillator. A phase difference is detected by a phase detector between the first and second frequency dividers and a first output pulse representative of the phase difference is produced when the second frequency divider is leading and a second output pulse representative of the phase difference is produced when the second frequency divider is lagging. A charge integrating circuit integrates the first and second output pulses to supply a phase difference signal to a lowpass filter which filters out high frequency components of the phase difference signal and operates the voltage-controlled oscillator. A first switch is provided for establishing a connection between the charge integrating circuit and the lowpass filter when it is turned on to operate the frequency synthesizer in a closed-loop mode and clearing the connection when the it is turned off to operate the frequency synthesizer in an open-loop mode. A second switch supplies power to the first and second frequency dividers during the closed-loop mode and interrupts the power during the open-loop mode. A control circuit is responsive to the first and second output pulses of the phase detector for detecting an initial phase difference which occurs between the first and second frequency dividers immediately after the frequency synthesizer enters the closed-loop mode and resetting one of the first and second frequency dividers so that the frequency dividers are aligned in phase. A gate circuit is connected between the phase detector and the charge integrating circuit for blocking the passages of the first and second output pulses of the phase detector to the charge integrating circuit when the initial phase difference is detected by the control circuit.


REFERENCES:
patent: 4980652 (1990-12-01), Tarusawa et al.
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5202906 (1993-04-01), Saito et al.
patent: 5471187 (1995-11-01)

Affiliated with

Also associated with

Rating

PLL frequency synthesizer using frequency dividers reset by... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL frequency synthesizer using frequency dividers reset by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL frequency synthesizer using frequency dividers reset by... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2523479