PLL frequency synthesizer circuit

Details PLL frequency synthesizer circuit PLL frequency synthesizer circuit

1993-09-16

1995-04-25

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1R, 331DIG2, 455260, H03D 324

Patent

active

054105714

ABSTRACT:
A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal. The circuit outputs a signal indicative of the frequency locked when the frequency difference is within the preset range, and outputs a signal indicative of the frequency unlocked when the difference of the frequency exceeds the preset range.

REFERENCES:
patent: 4272729 (1981-06-01), Riley, Jr.
patent: 4310805 (1982-01-01), Hackert et al.
patent: 4787097 (1988-11-01), Rizzo
patent: 4988955 (1991-01-01), Horie
patent: 5260979 (1993-11-01), Parker et al.

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