Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-07-10
2010-06-22
Payne, David C (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
07742554
ABSTRACT:
The invention provides a PLL device comprising a PFD unit, a charging pump circuit, a loop filter, an oscillator, a feedback divider and a current compensation circuit. The PFD unit measures a phase and a frequency difference between a reference clock signal and a feedback clock signal of the PLL device to output a difference signal UP and a difference signal DN. The charging pump circuit receives and transfers the difference signals UP and DN into a current. The loop filter receives and transfers the current into a voltage. The oscillator receives the voltage and outputs an output signal. The feedback divider having a parameter N receives the output signal to generate the feedback clock signal according to the parameter N, wherein a frequency of the feedback clock signal is N times a frequency of the output signal. When the reference clock signal leads the feedback clock signal, the current compensation circuit outputs a compensation current to the loop filter.
REFERENCES:
patent: 5892380 (1999-04-01), Quist
patent: 6570947 (2003-05-01), Zipper et al.
patent: 2005/0168292 (2005-08-01), Frans et al.
Chen Chien-Ming
Huang Chih-Chien
Haider Syed
Mediatek Inc.
Payne David C
Thomas Kayden Horstemeyer & Risley
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