PLL cycle slip detection

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S354000, C375S371000, C375S374000, C331S010000, C331S012000, C331S016000, C327S010000, C327S149000

Reexamination Certificate

active

07003065

ABSTRACT:
A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2π radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

REFERENCES:
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patent: 4901026 (1990-02-01), Phillips et al.
patent: 4902920 (1990-02-01), Wolaver
patent: 5890051 (1999-03-01), Hadjichristos et al.
patent: 6265902 (2001-07-01), Klemmer et al.
patent: 6441691 (2002-08-01), Jones et al.
patent: WO 9965146 (1999-06-01), None
patent: WO 02073806 (2002-09-01), None
Den Dulk R C: “Digital PLL Lock-Detection Circuit” Electronic Letters, IEEE Stevenage, GB, vol. 14, No. 24, Jul. 7, 1988, pp. 880-882, XP002078701 ISSN: 0013-5194.

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