PLL circuit and noise reduction means for PLL circuit

Details PLL circuit and noise reduction means for PLL circuit PLL circuit and noise reduction means for PLL circuit

1996-12-10

2001-06-19

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C375S316000, C375S215000, C331S011000

Reexamination Certificate

active

06249560

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a PLL circuit. More specifically, this invention relates to the technology of the PLL circuit for reducing a noise of a PLL frequency synthesizer.
Conventionally, for example,the invention disclosed in JP-A-127719/1992 has been used as a PLL circuit of this kind. The PLL circuit comprises a voltage controlled oscillator, a frequency divider for dividing an output signal of the voltage controlled oscillator, a phase comparator for comparing a phase of the output signal of the frequency divider and the phase of a reference clock and detecting the phase difference, a charge pump circuit driven by the output signal of the phase comparator, and a loop filter for smoothing output of the charge pump circuit. The PLL circuit controls the frequency of the voltage controlled oscillator based on the output voltage of the loop filter.
FIG. 4
shows the general composition of the PLL circuit disclosed in the JP-A-127719/1992. In
FIG. 4
, the numeral
1
is a phase comparator. The numeral
2
is a charge pump. The numeral
3
is a loop filter. The numeral
4
is a voltage controlled oscillator (referred to as VCO, hereinafter). The numeral
5
is a prescaler. The numeral
6
is a reference clock generation unit. The numeral
7
is a first frequency divider. The numeral
8
is a second frequency divider. The lower case a
1
is an output signal of the prescaler
5
(an input clock to the frequency divider
7
). The lower case b
1
is a reference clock of the reference clock generation unit
6
(an input clock to the frequency divider
8
). The lower case a
2
is an output signal of the frequency divider
7
(frequency divider output). The lower case b
2
is an output signal of the frequency divider
8
(frequency divider output).
In the PLL circuit, the output signal of the VCO
4
is divided by L by the prescaler
5
then divided by N by the frequency divider
7
. The reference clock from the reference clock generation unit
6
is divided by M by the frequency divider
8
. The upper cases L, M and N are natural numbers. The phase comparator
1
inputs the frequency divider output a
2
and b
2
and outputs the voltage proportionate to the phase difference of a
2
and b
2
. The charge pump
2
is driven according to the output voltage of the phase comparator
1
. The loop filter
3
smoothes output of the charge pump
2
and making the output a control voltage of the VCO
4
. In this way, the PLL (a phase lock loop) is composed and negative feedback is applied to the phase comparator
1
in order to stabilize the input phase difference. The output frequency f
0
of the VCO
4
here is calculated as follows; f
0
=f
r
×N·L/M. In this expression, f
r
indicates the generation frequency of the reference clock generation unit
6
.
However, in the conventional PLL circuit like this, the frequency divider outputs a
2
and b
2
are directly used as an input signal of the phase comparator
1
. Therefore the PLL circuit directly suffers from the effects caused by grand bounce and overshoot generated when a logic value in the frequency divider
7
or
8
is inversed and a great phase noise is added to output of the VCO
4
.
The process is explained, referring to
FIGS. 5
from A to E. The
FIG. 5A
shows the input clocks a
1
and b
1
to the frequency dividers
7
and
8
. The
FIG. 5B
shows the frequency divider outputs a
2
and b
2
from the frequency dividers
7
and
8
. When the frequency divider
7
or
8
is triggered by the rising edge of the input clock a
1
or b
1
(at t1 in FIG.
5
A), the frequency divider output signal a
2
or b
2
changes a little later (at t2 in FIG.
5
B).
FIG. 5C
shows a noise caused by grand bounce and overshoot generated when a logic value in the frequency divider
7
or
8
is inversed. The noise is logically generated right after the input clocks a
1
and b
1
to the frequency dividers
7
and
8
are activated and coincidentally the frequency divider output signals a
2
and b
2
change. Therefore, as illustrated in the enlarged diagrams in
FIGS. 5D and E
, the effects produced by the noise generated in the frequency dividers
7
and
8
make the jitters in the phase of the frequency divider output signals a
2
and b
2
. As a result, when the phases are compared and the PLL is operated here, an extra noise element as well as natural output is included in output of the VCO
4
as illustrated in FIG.
6
.
SUMMARY OF THE INVENTION
The objective of the present invention is to solve the above-mentioned tasks.
Moreover, the objective of the invention is to provide the technology of a PLL circuit by which a phase noise added to output of a voltage controlled oscillator generated by a noise of a frequency divider is drastically reduced.
The objective of the present invention is achived by a noise reduction method of reducing a noise in a PLL circuit made by a frequency divider, said noise reduction method comprising: a clock signal generation step of generating a clock signal corresponding to an input control voltage; a frequency dividing step of dividing said clock signal simultaneously with being triggered by any of rising edge and falling edge of said clock signal and generating a first dividing signal; a delay step of taking said first dividing signal and delaying said dividing signal simultaneously with being triggered by one, that is not used as a trigger of said frequency dividing step, of said rising edge and falling edge of said clock signal; a reference clock generation step of generating a reference clock of a reference frequency; and a control voltage generation step of generating a control voltage corresponding to a phase difference between said delayed dividing signal and said reference clock.
Furthermore, the objective of the present invention is achived by a noise reduction method of reducing a noise in a PLL circuit made by a frequency divider, said noise reduction method comprising: a clock signal generation step of generating a clock signal corresponding to an input control voltage; a first frequency dividing step of dividing said clock signal for prescaling and generating a first dividing signal; a second frequency dividing step of dividing said first dividing signal simultaneously with being triggered by one of said rising edge and falling edge of said first dividing signal and generating said second dividing signal; a delay step of delaying said second dividing signal simultaneously with being triggered by one of said rising edge and falling edge of said second signal not used as a trigger of said frequency dividing step; a reference clock generation step of generating a reference clock of a reference frequency; and a control voltage generation step of generating a control voltage corresponding to a phase difference between said delayed second dividing signal and said reference clock.
In the abovementioned method, the noise reduction method may further comprise a a third frequency dividing step of dividing said reference clock simultaneously with being triggered by any of rising edge and falling edge of said reference clock signal and outputting said third dividing signal; and a second delay step of delaying and outputting said third dividing signal simultaneously with being triggered by one of said rising edge and falling edge of said reference clock signal not used as a trigger of said third frequency dividing step, and wherein said control voltage generation step comprises a step of generating a control voltage corresponding to a phase difference between said delayed second dividing signal and said delayed third dividing signal.
To realize the above-mentioned method, the first PLL circuit comprises voltage control oscillation means, frequency dividing means triggered by any of rising edge and falling edge of an output signal of the voltage control oscillation means for dividing and outputting the output signal of the voltage control oscillation means, flip-flop means triggered by one of the rising edge and falling edge of the output signal of the voltage control oscillati

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