PLL circuit and method

Details PLL circuit and method PLL circuit and method

1996-04-12

1998-06-16

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 327156, H03D 324

Patent

active

057683263

ABSTRACT:
A PLL circuit for use in a digital broadcasting receiver includes a receiver for receiving a bit stream containing program clock references (PCRs) transmitted from a broadcast station. The PCRs correspond to a frequency and phase of a transmitter system clock. The circuit also contains an oscillator for generating receiver system clocks, a counter responsive to the system clocks, and a connection to allow the bit stream to flow from the receiver to the oscillator. A controller controls the counter based on differences between the PCRs in the bit stream and the counter output. A load control means successively loads the PCRs on the counter in their order of transmission to lock the frequency and phase of the receiver system clock provided from the oscillator with the frequency and phase of the transmitter system clock. This arrangement allows quick adjustment of the receiver system clock frequency and phase by removing the influence of the insertion intervals of the PCRs in the bit stream when making the adjustment.

REFERENCES:
patent: 5287182 (1994-02-01), Haskell et al.
patent: 5543853 (1996-08-01), Haskell et al.
"System Time Clock Recovery in the Decoder", ISO/IEC 13818-1, ANNEX 3, D.0.3, ISO/IEC JTC1/SC29/WG11: Nov. 13, 1994, pates 112-115.

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