PLL circuit and its automatic adjusting circuit

Details PLL circuit and its automatic adjusting circuit PLL circuit and its automatic adjusting circuit

1997-09-04

2000-06-20

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 327159, H03D 324

Patent

active

060786337

ABSTRACT:
A 1/N programmable frequency divider for dividing the frequency of an output clock CLK1 from a VCO is connected between the VCO and a phase comparator in a PLL circuit. An adjusting circuit includes a counter for detecting a half-value of the frequency and for addressing a table ROM to make it read out a program data N and target value TV, a counter for detecting a half-value of the frequency of the output clock CLK from the 1/N programmable frequency divider, a digital comparator for comparing the count value of the counter and the target value TV and an up/down counter for incrementing or decrementing is count CFV in accordance with the comparison result, the count CFV being provided to the control input of the VCO.

REFERENCES:
patent: 4272729 (1981-06-01), Riley, Jr.
patent: 4528523 (1985-07-01), Crowley
patent: 5614870 (1997-03-01), Sauer et al.

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