PLL circuit

Details PLL circuit PLL circuit

1998-12-04

2002-04-23

Pham, Chi (Department: 2731)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S505000

Reexamination Certificate

active

06377647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit that causes an internal oscillation signal to lock to an external input clock signal and, more particularly, to a PLL circuit suitable for use in a high-speed data modem.
2. Description of the Related Art
Usually, data modems are used for the transmission of data over telephone lines, leased lines, or metallic lines. Among them, data modems for use over metallic lines have improved greatly in terms of speed and, nowadays, data rates of several Mbps can be achieved. When using such a high-speed data modem by connecting it to a network-synchronized device via a digital multiplexer or the like, the modem must take as an input a high-speed network clock supplied in the form of a clock signal (ST
1
) from an external device, and cause its internal oscillation signal to lock to the high-speed clock.
FIG. 8
is a block diagram showing one example of a prior art PLL circuit for ST
1
in a data modem. In the figure, a microprocessor (MPU)
31
, to which the output of an oscillator
32
is input, judges the phase advance or delay of the output clock signal FBO
3
of the PLL circuit relative to the input clock signal ST
1
and performs a first-order PLL operation to increase or decrease the machine cycle used to create the output clock signal FBO
1
of the MPU. Likewise, a digital signal processor (DSP)
33
, to which the output of an oscillator
34
is input, judges the phase advance or delay of FBO
3
relative to FBO
1
and performs a second-order PLL operation to increase or decrease the machine cycle used to create the output clock signal FBO
2
of the DSP. A clock generating circuit
35
generates various clocks such as the multi-chip synchronization clock FBO
3
, D/A conversion clock, etc.
In the ST
1
PLL circuit described above, because of its operating principle, jitter equivalent to at least plus or minus one machine cycle of the DSP can occur in the D/A conversion clock. The DSP machine cycle is about 30 ns to 100 ns. Accordingly, such jitter is too large for data rates of several Mbps and can cause data errors in data transmission.
SUMMARY OF THE INVENTION
In view of the above situation, it is an object of the present invention to provide a PLL circuit capable of suppressing the jitter to a level lower than that attainable with the prior art.
To achieve the above object, according to the present invention, there is provided a PLL circuit for controlling the phase of an internal clock source based on a timing signal extracted from a received signal, comprising: a missing-pulse clock signal creation circuit for creating, based on an output signal of the clock source, a missing-pulse clock signal having a periodic missing-pulse portion; a phase comparator circuit for sampling the timing signal by using the missing-pulse clock signal; and a processing circuit for converting a signal value output from the phase comparator circuit into a phase difference, and for controlling the phase of the clock source based on the phase difference.
According to the present invention, there is also provided a data modem incorporating, as a circuit for achieving synchronization with a received signal from an external device, a PLL circuit that controls the phase of an internal clock source based on a timing signal extracted from the received signal, the PLL circuit comprising: a missing-pulse clock signal creation circuit for creating, based on an output signal of the clock source, a missing-pulse clock signal having a periodic missing-pulse portion; a phase comparator circuit for sampling the timing signal by using the missing-pulse clock signal; and a processing circuit for converting a signal value output from the phase comparator circuit into a phase difference, and for controlling the phase of the clock source based on the phase difference.
According to the present invention, there is also provided a phase control method for discriminating an excursion in the phase of a clock signal output from an internal clock source relative to the phase of a timing signal extracted from a received signal, and for controlling the phase of the clock signal relative to the phase of the timing signal, based on the result of the phase excursion discrimination, comprising the steps of: creating from the clock signal a missing-pulse clock signal having a clock signal OFF period periodically alternating with a clock signal ON period; sampling the timing signal by using the missing-pulse clock signal; and discriminating the phase excursion of the clock signal relative to the timing signal, based on the ON/OFF state of the timing signal during the ON period of the missing-pulse clock signal.


REFERENCES:
patent: 5428648 (1995-06-01), Fukuda
patent: 5610952 (1997-03-01), Yamanaka et al.
patent: 5740211 (1998-04-01), Bedrosian
patent: 5878101 (1999-03-01), Aisaka
patent: 5892405 (1999-04-01), Kamikubo et al.
patent: 6031425 (2000-02-01), Hasegawa
patent: 6236278 (2001-05-01), Olgaard
patent: 62-43215 (1987-02-01), None
patent: 6-104741 (1994-04-01), None

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