PLL circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

331 34, H03D 324

Patent

active

055815847

ABSTRACT:
A PLL circuit includes a PLLic formed into an integrated circuit; a loop filter for receiving an output signal from the PLLic; a voltage-controlled oscillator having an oscillation frequency which is controlled according to an output signal of the loop filter for applying a controlled oscillation output signal to the PLLic, the voltage-controlled oscillator including a resonator and a negative resistor circuit; wherein a buffer amplifier functioning as a part of the voltage-controlled oscillator is incorporated into the PLLic, and the resonator and the negative resistor circuit of the voltage-controlled oscillator are disposed outside of the PLLic.

REFERENCES:
patent: 5218325 (1993-06-01), Trelewicz et al.

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