PLL circuit

Details PLL circuit PLL circuit

1994-05-24

1995-10-17

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375374, H03D 324

Patent

active

054597552

ABSTRACT:
There is disclosed a PLL circuit wherein a delay circuit (3') of a phase comparator (30') receives a supply current (IC) from a first variable current source (.PHI.IC) and changes a delay time (.DELTA.T) in negative correlation with the amount of the supply current (IC), and the first variable current source (.PHI.IC) changes the amount of the supply current (IC) to the delay circuit (3') in accordance with the indication of a control signal (C1) serving as a supply current control signal for a second variable current source (.PHI.IA) and a third variable current source (.PHI.IB) of a charge pump circuit (31). Changes in delay time of the delay device of the phase comparing device are adapted such that the delay time is constantly suitable as the amount of current of the phase comparison voltage signal of the charge pump circuit changes, permitting reduction in lock-up time.

REFERENCES:
patent: 4814726 (1989-03-01), Byrd et al.
patent: 5144156 (1992-09-01), Kawasaki
Iga et al. U.S. application Ser. No. 08/079,758 Jun. 22, 1993.

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