Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-05-08
2001-05-15
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C331S00100A, C331S018000, C327S156000
Reexamination Certificate
active
06233297
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a reception destuff circuit for use in an SDH (Synchronous Digital Hierarchy) network. More particularly, this invention relates to a complete secondary DPLL (Digital Phase Locked Loop) for use in stuff-synchronizing in an SDH network.
DESCRIPTION OF THE RELATED ART
In an SDH (Synchronous Digital Hierarchy) network, for frequency regulation for a high speed side clock, a pointer operation which uses byte stuffing has been adopted. Namely, a stuff pulse is stuffed on a data transmitting side, and the stuffed pulse is destuffed on a data receiving side. The transmitted data is temporarily memorized in a memory on the data receiving side, and is then read out by the low-speed side signal on the data receiving side.
In the pointer operation, a phase difference or error may occur as a result of the byte stuffing. Phase differences of 8 [UI/time] can be generated in every pointer operation. To obtain a low-speed side clock signal from a high-speed side clock signal, the phase caused by the pointer operation, i.e., stuffing and destuffing of the stuff pulse, should be minimized. Thus, the low-speed side clock signal in which the phase difference is minimized is used to read out data from the memory. Namely, in order to obtain a low speed side clock signal from a high speed side clock signal, it is necessary to provide a destuff circuit for minimizing a phase difference generated due to a pointer operation, namely insertion or elimination of a stuff pulse.
Generally, a PLL (Phase Locked Loop) is used for the destuff circuit. However, when the signal with a phase difference is input to the PLL (Phase Locked Loop), at the time of phase comparison with a signal which does not have a phase difference at the output side, a phase error occurs. Namely, in general, when data is read out from the memory, the destuff circuit using the PLL (phase-locked loop) has been used. However, when a signal with a phase difference is input to the PLL, a phase error occurs when comparing it with an output signal with no phase difference.
There is a destuff circuit adopting a complete secondary system DPLL for decreasing the phase error.
FIG. 1
is a view showing a constitution of the conventional destuff circuit adopting a complete secondary system DPLL. Referring to
FIG. 1
, the destuff circuit adopting a complete secondary system DPLL comprises a primary loop which includes a frequency regulator
1
for regulating a frequency by increasing or decreasing a pulse or pulses to or fro a reference clock signal, an R frequency divider
2
for dividing the frequency of the frequency-regulated reference clock by R to output a low-speed side clock signal, N frequency dividers
3
-
1
and
3
-
2
for dividing by N the frequencies of a high-speed side clock signal and the low-speed side clock signal, a multi-valued phase comparator
4
for comparing the phases output from the N frequency dividers
3
-
1
and
3
-
2
to output a leading phase pulse which represents the number of phase leads accumulating to a phase difference of 180° and a lagging phase pulse which represents the number of phase lags accumulating to a phase difference of 180°, a primary random walk filter
5
for dividing by N1 the difference between pulse numbers of the leading phase and the lagging phase output from the multi-valued phase comparator
4
, and an adder-subtractor circuit
9
for providing the frequency regulator
1
with a control pulse.
In addition, the complete secondary system DPLL further comprises a secondary loop which includes a secondary random walk filter
6
for dividing by N2 the pulse number output from the primary random walk filter
5
, a Q counter
7
for storing the output of the secondary random walk filter
6
, a rate multiplier
8
for producing increment pulses or decrement pulses according to the low-speed side clock signal and a central frequency of the system, thus outputting selected increment and decrement pulses according to the values stored in the Q counter
7
, and the adder-subtractor circuit
9
for increasing or decreasing the output of the primary random walk filter
5
according to the output of the rate multiplier
8
to provide the frequency regulator
1
with a control pulse for increasing or decreasing the frequency of regulator
1
.
In the conventional destuff circuit adopting a complete secondary system DPLL, the secondary loop causes the low-speed side clock signal to operate at the central frequency of the system which is stored therein. The destuff circuit as described-above does not generate a steady-state phase error during operation at the stored central frequency of the system.
Namely, the steady-state phase error is generated because, when the frequency of the high-speed side clock signal is shifted to the frequency of the reference clock signal of the PLL, the steady-state phase error causes the PLL to lock to the frequency of the high-speed side clock signal. The steady-state phase error is generated when the primary loop causes the control pulse to be applied to the frequency regulator
1
. However, the steady-state phase error is not generated due to the control pulse of the primary loop because the secondary loop applied the control pulse to the frequency regulator
1
during operation at the stored central frequency of the system.
However, there are problems in that the development costs spent for respective interface units, the time scheduled for development, and so forth are increased because the DPLL circuit is incapable of being used in common with each other, since it is necessary to design the DPLL circuit separately for 2M (megahertz) and for 1.5M (megahertz), in the interface unit providing a 2M interface and a 1.5M interface of the transmission communication apparatus for the destuff circuit adopting a conventional complete secondary system DPLL.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the invention to provide a PDH (Plesiochronous Digital Hierarchy) low-speed signal switching DPLL (Digital Phase-Locked Loop) system, in which it is unnecessary to design the DPLL circuit individually for respective different frequency interface units, in a destuff circuit adopting a complete secondary system DPLL which is applicable to a PDH low-speed signal interface unit of the transmission communication apparatus.
In one arrangement described below by way of example in illustration of the invention, a PDH low-speed signal switching DPLL system, which is a destuff circuit using a complete secondary system DPLL comprising a primary loop which includes a frequency regulator for regulating the frequency so as to add or eliminate a pulse(s) to or from a reference clock signal, an R frequency divider for outputting a low speed side clock signal by dividing by R the reference clock signal being subjected to frequency regulation, first and a second N frequency dividers for dividing by N a high speed side clock signal and a low speed side clock signal respectively, a multi-valued phase comparator for comparing the phases output from the first and the second N frequency dividers to output a leading phase pulse which represents the number of phase leads accumulating to a phase difference of 180° and a lagging phase pulse which represents the number of phase lags accumulating to a phase difference of 180°, a primary random walk filter for dividing by N1 the difference between pulse numbers of the leading phase and lagging phase outputs from the multi-valued phase comparator, and an adder-subtractor circuit for providing the frequency regulator with a control pulse, and in addition thereto a PDH low-speed signal switching DPLL system, which is a destuff circuit using a complete secondary DPLL system comprising a secondary loop which includes a secondary random walk filter for dividing by N2 a pulse number output from the primary random walk filter, a Q counter for storing an output of the secondary random walk filter, a rate multiplier for producing some increment pulses or decrement pulses accordin
Chin Stephen
Deppe Betsy L.
NEC Coporation
Scully Scott Murphy & Presser
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