PLDs providing reduced delays in cascade chain circuits

Details PLDs providing reduced delays in cascade chain circuits PLDs providing reduced delays in cascade chain circuits

2005-03-08

2005-03-08

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06864714

ABSTRACT:
The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.

REFERENCES:
patent: 5258668 (1993-11-01), Cliff et al.
patent: 6359469 (2002-03-01), Mendel et al.

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