PLD with split multiplexed inputs from global conductors

Electronic digital logic circuitry – Multifunctional or programmable – Array

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329 39, H03K 19177

Patent

active

059429143

ABSTRACT:
An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer. A second-level multiplexer connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about 1/3.

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