Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2001-03-26
2002-03-05
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S189080
Reexamination Certificate
active
06353552
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention is integrated circuits for implementing reconfigurable logic, such as field programmable gate arrays (“FPGAs”), that are specially designed for emulation systems. In particular, the present invention is directed to a FPGA having multiple blocks of multiported memory and a special port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state.
BACKGROUND OF THE INVENTION
Field programmable gate arrays such as those available from Xilinx, Altera, AT&T and others are widely used for implementing various types of logic functions. FPGAs offer an advantage over mask-programmed gate arrays and discrete logic because the logic functions carried out by an FPGA can be easily reprogrammed to meet the user's objectives.
FPGAs are traditionally structured in a multi-level hierarchy, with simple logic blocks capable of performing the desired logic functions combined together to form more complex blocks, which are then combined to form a complete chip. Designs intended for implementation in FPGAs often include memories. This is especially true in prototyping applications where the designs being prototyped often contain large and complex memories.
Some FPGAs provide a mechanism for implementing small amounts of memory. For example, the Xilinx 4000 series of FPGAs allow the user to implement thirty-two bits of random-access memory (“RAM”) for each configurable logic block (“CLB”). RAMs can also be constructed using the flip-flop storage elements in the CLBs. Combining these small RAMs into the larger memories found in real designs, however, is difficult, slow, and consumes much of the FPGA routing and logic resources. This problem is particularly severe when the memory to be implemented has multiple ports, especially multiple write ports which require even greater routing resources to satisfy the memory requirements. Routing of memory outputs additionally should not require a sizable expansion in the routing network. A further drawback of the existing devices is the lack of an easy way to observe the contents of the FPGA memories at a selected point in time or to initialize the memories to a predetermined state. The prior art has not effectively resolved these and other issues.
SUMMARY OF THE INVENTION
A first, separate aspect of the present invention is a memory for an integrated circuit for implementing reconfigurable logic where the memory allows flexible implementation of various types of large and multiported memories inside the integrated circuit.
A second, separate aspect of the present invention is a multiported memory for an integrated circuit for implementing reconfigurable logic.
A third, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic having a memory whose width and depth are configurable in a tradeoff fashion.
A fourth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic, where the integrated circuit includes a multiported memory wherein the width and depth of each port may be configured independently of the width and depth of the other ports.
A fifth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic and including a memory, where the memory includes a register that can read the contents of the memory synchronously such that the data read accurately represents a snapshot of the memory contents at a point in time.
A sixth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic and including a memory, where the memory includes a register that can load data into the memory so that the memory is loaded to a predetermined state.
A seventh, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic, where the circuit includes a logic element, an interconnect network and a memory that uses the logic element to access the interconnect network, thereby alleviating the necessity of adding routing lines to the interconnect network just to satisfy the memory requirements.
An eighth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic, where the circuit includes a logic element, an interconnect network and a memory that shares some but not all of the routing resources used by the logic element so that the logic element may still perform logic functions.
One exemplary embodiment of the present invention provides a field programmable gate array integrated circuit including a logic element programmably configurable to implement user-defined logic functions, and a configurable memory block coupled to the logic element. The memory is capable of being written to and read from, and has a configurable width and a configurable depth. If the width of the memory is increased, its depth is correspondingly decreased, similarly, if the width is decreased the depth is increased. The memory block includes a write buffer having a plurality of data inputs, a plurality of select lines for selecting one of the plurality of data inputs, a first logic gate having an input coupled to the selected one of the plurality of data inputs, a second logic gate coupled to the select lines, and a third logic gate having an input coupled to an output of the second logic gate.
Another embodiment of the present invention provides a field programmable gate array integrated circuit having a logic element programmably configurable to implement user-defined combinatorial or registered logic functions. Also included are a look-up table providing a look-up table output, and a register coupled to the look-up table output and providing a register output. The look-up table output or the register output may be provided as a logic element output. A memory block to store data is coupled to the logic element output, and the memory block includes a write buffer circuit having at least three data inputs, selectively coupled to a first NOR gate by using at least three select inputs, a first logic gate, which receives the select inputs and provides a first logic gate output to the first NOR gate, and a second NOR gate, which receives the first logic gate output.
Further exemplary methods and apparatus of the present invention provide for the initialization and determination of the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.
Yet another embodiment of the present invention provides a method of determining the contents of a memory block in a programmable logic device. The method includes providing the memory block having a plurality of memory storage cells and a corresponding plurality of shadow cells. Data is stored in the plurality of memory storage cells, and transferred to the corresponding plurality of shadow cells. Once transferred, the data is stored in the plurality of shadow cells. The data is then read from the plurality of shadow cells.
REFERENCES:
patent: 5581198 (1996-12-01), Trimberger
patent: 5764079 (1998-06-01), Patel et al.
patent: 5986962 (1999-11-01), Bertin et al.
patent: 6020758 (2000-02-01), Patel et al.
patent: 6034886 (2000-03-01), Chan et al.
Butts Michael R.
Chen Chao Chiang
Norman Kevin A.
Patel Rakesh H.
Sample Stephen P.
Altera Corporation
Nguyen Tan T.
Townsend and Townsend / and Crew LLP
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