Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-12
2006-09-12
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07107565
ABSTRACT:
Structures and methods of representing programmable PLD hardware tiles including common routing resources common to all of the hardware tiles and unique logic resources unique to each hardware tile. A software representation of the programmable hardware tiles includes a common software tile including a description of the common routing resources, and, for each hardware tile, a unique software tile including a description of the unique logic resources included in the hardware tile. The common software tile has first terminals for coupling an instance of the common software tile to other instances of the common software tile, and also has second terminals. The unique software tile includes terminals for coupling the unique software tile to the second terminals of an instance of the common software tile. The software representation can also include a PLD device model that utilizes a uniform numbering scheme based on numbered instances of the common software tile.
REFERENCES:
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patent: 6396303 (2002-05-01), Young
patent: 2004/0010767 (2004-01-01), Agrawal et al.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 19-71.
Bean Keith R.
Lindholm Jeffrey V.
Cartier Lois D.
Dinh Paul
Mannu Leroy D.
Xilinx , Inc.
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