PLD configuration port architecture and logic

Details PLD configuration port architecture and logic PLD configuration port architecture and logic

2000-09-29

2004-06-08

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

C716S030000, C711S170000, C326S039000, C710S001000

Reexamination Certificate

active

06748456

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for programmable logic devices generally and, more particularly, to a programmable logic device configuration port architecture and logic.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
The arrangement and operation of components within the PLD are programmed by architecture configuration bits. The architecture configuration bits are set prior to normal operation of a PLD. The bits are set using an operation called “programming” or “configuration”. The configuration bits can be stored in volatile memory (i.e., SRAM) or non-volatile memory (i.e., EEPROM/flash). When the configuration bits are stored in volatile memory, the configuration bits need to be loaded from an off-chip non-volatile memory, a micro controller, or some other source.
SUMMARY OF THE INVENTION
The present invention concerns a programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the PLD in response to the data.
The objects, features and advantages of the present invention include providing a programmable logic device configuration port architecture and logic that may (i)provide flexible configuration capabilities, (ii) use data compression,


REFERENCES:
patent: 5764076 (1998-06-01), Lee et al.
patent: 6172520 (2001-01-01), Lawman et al.
patent: 6255849 (2001-07-01), Mohan
patent: 6304101 (2001-10-01), Nishihara
patent: 6308311 (2001-10-01), Carmichael et al.
patent: 6327634 (2001-12-01), Statovici

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