Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-27
2003-05-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06567970
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for configuring programmable logic devices generally and, more particularly, to a method and/or architecture for programming configuration bits of programmable logic devices.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
The arrangement and operation of components within the PLD are programmed by architecture configuration bits. The architecture configuration bits are set prior to normal operation of a PLD. The configuration bits can be stored in volatile memory (i.e., SRAM) or non-volatile memory (i.e., EEPROM/flash). The bits are set using an operation called “programming” or “configuration”.
Conventional configuration memories organize the configuration bits in a single rectangular array. The array is programmed by loading appropriate values into a set of row and column address registers. Either a single central controller or an external programmer controls the configuration operations. The controller or external programmer must also keep track of all configuration bit counts.
The number of configuration bits can vary from one device to another, even within the same device family. Different numbers of configuration bits require different array geometries. Because the external programmer/controller must keep track of bit counts, programming different devices, even of the same family, requires complicated programming in the external controller/programmer.
A configuration memory and control architecture that is easy to scale and program for different devices would be desirable.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising one or more configuration blocks. The configuration blocks (i) may comprise a number of configuration elements and. (ii) may be configured to initiate reading or writing of the configuration elements in response to a control input.
The objects, features and advantages of the present invention include providing a method and/or architecture for programming configuration bits of programmable logic devices that may (i) provide full chip configuration, (ii) provide a fully scalable configuration architecture, (iii) speed up programming times, (iv) organize configuration elements in relatively small autonomous configuration blocks, (v) use global input lines, (vi) use PLD type blocks and/or embedded RAM blocks as configuration blocks, (iv) simplify programming, and/or (v) provide a programming scheme that may be independent of device type and family.
REFERENCES:
patent: 4717914 (1988-01-01), Scott
patent: 5745734 (1998-04-01), Craft et al.
patent: 5881254 (1999-03-01), Corrigan et al.
patent: 6216259 (2001-04-01), Guccione et al.
patent: 6219824 (2001-04-01), Borland
patent: 6259271 (2001-07-01), Couts-Martin et al.
patent: 6304101 (2001-10-01), Nishihara
patent: 6363519 (2002-03-01), Levi et al.
patent: 6421817 (2002-07-01), Mohan et al.
Ighani Ramin
Lulla Navaz
Nayak Anup
Nema Rajiv
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Miller Robert M.
Siek Vuthe
Tat Binh
LandOfFree
PLD configuration architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with PLD configuration architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLD configuration architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3016661