Plating structure for a pin grid array package

Chemistry: electrical and wave energy – Apparatus – Electrolytic

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

204297R, 205 78, 205122, 29825, C25D 1704

Patent

active

060511192

ABSTRACT:
Disclosed is a plating structure including a substrate having a plurality of pins to be plated and a metallic plating screen having a plurality of apertures, wherein each of the apertures has at least two tabs spaced apart from each other, wherein the metallic plating screen is placed over the pins so that at least two pins penetrate each aperture, each of the pins contacting a tab of the aperture. Also disclosed is a method of electrolytically plating a plurality of pins utilizing the above metallic plating screen.

REFERENCES:
patent: 4949455 (1990-08-01), Nakamura et al.
patent: 5022976 (1991-06-01), Roll et al.
patent: 5087331 (1992-02-01), Roll et al.
patent: 5342992 (1994-08-01), Noto
patent: 5516416 (1996-05-01), Canaperi et al.
patent: 5580432 (1996-12-01), Shibata et al.
patent: 5869139 (1999-02-01), Biggs et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Plating structure for a pin grid array package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Plating structure for a pin grid array package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plating structure for a pin grid array package will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2333853

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.