Plateline driver with RAMP rate control

Details Plateline driver with RAMP rate control Plateline driver with RAMP rate control

2004-12-03

2008-03-25

Phan, Trong (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S226000

Reexamination Certificate

active

07349237

ABSTRACT:
A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

REFERENCES:
patent: 5978251 (1999-11-01), Kraus et al.
patent: 6584009 (2003-06-01), Roehr et al.
patent: 6667896 (2003-12-01), Rickes et al.
patent: 6671199 (2003-12-01), Maruyama
patent: 6819601 (2004-11-01), Eliason et al.
patent: 6906943 (2005-06-01), Kang
patent: 6906945 (2005-06-01), Madan
patent: 6950326 (2005-09-01), Suzuki
patent: 6980460 (2005-12-01), Shiratake et al.
patent: 7064972 (2006-06-01), Takashima

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