Plate potential applying structure of trench capacitor cell

Details Plate potential applying structure of trench capacitor cell Plate potential applying structure of trench capacitor cell

1996-03-21

1997-12-16

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257304, 257534, 257622, 257906, 257908, 36518905, 36523001, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

056988788

ABSTRACT:
A DRAM cell includes first and second trenches formed in a P-type silicon substrate, a first N-type diffusion layer formed around the first trench, and a second N-type diffusion layer formed around the second trench, contacting the first N-type diffusion layer, and reaching the surface of the substrate. In the first trench, a storage node electrode whose capacitance is coupled to the first N-type diffusion layer and a conductive polysilicon film for leading the storage node electrode to the surface of the substrate are provided. One of source and drain regions of each cell transistor is connected to the conductive polysilicon film. The first N-type diffusion layer is connected to the second N-type diffusion layer, and the second diffusion layer is connected to a plate potential supply-line.

REFERENCES:
patent: 4918502 (1990-04-01), Kaga et al.
patent: 5293347 (1994-03-01), Ogawa
patent: 5377151 (1994-12-01), Komuro
patent: 5432365 (1995-07-01), Chin et al.
IEEE Transactions on Electron Devices, vol. 35, No. 8, pp. 1257-1263, Half-V.sub.cc Sheath-Plate Capacitor DRAM Cell With Self-Aligned Buried Plate Wiring, T. Kaga et al, Aug. 1988.
International Electron Devices Meeting 1993, pp.627-630, A 0.6 .mu.m.sup.2 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), L. Nesbit et al., Dec. 5-8, 1993.

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