Plastic sealed multiple level metalization semiconductor device

Details Plastic sealed multiple level metalization semiconductor device Plastic sealed multiple level metalization semiconductor device

1994-03-10

1995-09-05

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257759, 257765, 257767, H01L 2348, H01L 2946, H01L 2954, H01L 2962

Patent

active

054481120

ABSTRACT:
A plastic sealed semiconductor device designed to prevent sliding of wiring due to thermal stress is disclosed. A lower layer wiring is provided adjacent to an outside of a portion of an uppermost layer of wiring covered by a cover film, which is arranged closest to an outer periphery of the semiconductor chip. Compressive stress of the sealing resin is divided by a step portion due to the uppermost layer of wiring and a step portion due to the lower layer of wiring. Further, since the interlayer insulating film covering the lower layer of wiring is flattened, the step portions are inclined gently in which stress is further divided. Therefore, the sliding of wiring is reliably prevented.

REFERENCES:
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5117280 (1992-05-01), Adachi

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