Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-12-10
2001-05-01
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S664000, C257S758000
Reexamination Certificate
active
06225690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the packaging of semiconductor devices, and in particular to a ball grid array (BGA) package.
2. Description of the Related Art
BGA packages for semiconductor devices are becoming increasingly common. A cross-section of one conventional plastic BGA (PBGA) package is illustrated in FIG.
1
. As shown, the package comprises a semiconductor device
10
mounted on a substrate
12
and electrically connected to traces (not shown) on the substrate
12
through bonding wires
14
. Solder balls
16
serve to mount the package to a printed circuit board. The traces are connected to the solder balls
16
through vias
17
in the substrate. The substrate
12
comprises three material layers
20
,
22
and
24
, which comprise pre-preg, a core which is typically BT resin and pre-preg, respectively; the pre-preg thickness is approximately 0.100 mm while the core thickness is approximately 0.500 mm.
The three material layers
20
,
22
and
24
define four metal layers,
26
,
28
,
30
and
32
. Layer
26
comprises a plurality of traces for signal input/output (I/O) and layer
28
comprises a metal plane which serves as a reference (ground) to the traces on layer
26
. The traces on layer
26
may also be routed underneath the die. All of the traces on layer
26
, whether or not routed underneath the die, are connected by vias to layer
32
, where signal traces connect vias to the desired solder balls. Layer
30
comprises a partial ground plane and a partial power plane wherein the partial ground plane serves as a reference to the traces on layer
32
. (The partial ground plane is generally directly above the traces for which it is serving as a reference while the power plane may be, for example, a ring that surrounds the ground plane and is not directly above any of those traces.)
It is desirable to improve upon various characteristics package illustrated in FIG.
1
. In particular, the traces on layers
26
and
32
are referenced only by one plane, such that current is by one plane. It would be desirable to increase cross talk immunity of traces (i.e. immunity of signal traces carrying current to interference from adjacent current carrying traces).
SUMMARY OF THE INVENTION
These and other needs are met by the present invention, which comprises a package with multiple routing layers. In particular, according to one embodiment, the present invention comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers. Traces on one of the layers are between a power plane and a ground plane such that a strip line configuration results. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connected to the solder balls through vias and possibly through routing on another metal layer.
The strip line configuration improves the cross talk immunity of traces.
REFERENCES:
patent: 4875087 (1989-10-01), Miyauchi et al.
patent: 5036163 (1991-07-01), Spielberger et al.
patent: 5089878 (1992-02-01), Lee
patent: 5625225 (1997-04-01), Huang et al.
patent: 5640048 (1997-06-01), Selna
patent: 5708296 (1998-01-01), Bhansali
patent: 5714801 (1998-02-01), Yano et al.
patent: 5763947 (1998-06-01), Bartley
patent: 5847936 (1998-12-01), Forehand et al.
patent: 5886406 (1999-03-01), Bhansali
patent: 5898217 (1999-04-01), Johnston
patent: 5990547 (1999-11-01), Sharma et al.
patent: 6008534 (1999-12-01), Fulcher
patent: 6064113 (2000-05-01), Kirkman
Juneja Nitin
Thurairajaratnam Aritharan
Clark Sheila V.
Hopenfeld Bruce R.
LSI Logic Corporation
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