Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-25
2003-12-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S534000, C438S637000, C438S643000, C438S653000, C438S677000, C438S687000, C438S710000, C438S714000
Reexamination Certificate
active
06656832
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming conductor layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced electrical properties, conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to form within microelectronic fabrications patterned microelectronic conductor layers of copper containing conductor materials. Patterned microelectronic conductor layers formed within microelectronic fabrications of copper containing conductor materials are desirable in the art of microelectronic fabrication insofar as patterned microelectronic conductor layers formed of copper containing conductor materials generally provide improved electrical performance in comparison with patterned microelectronic conductor layers formed of other conductor materials, such as but not limited to aluminum containing conductor materials.
While patterned microelectronic conductor layers formed of copper containing conductor materials are thus clearly desirable in the art of microelectronic fabrication, patterned microelectronic conductor layers formed of copper containing conductor materials are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, patterned microelectronic conductor layers formed of copper containing conductor materials are often difficult to form within microelectronic fabrications with optimized and enhanced electrical properties.
It is thus desirable in the art of microelectronic fabrication to form within microelectronic fabrications patterned microelectronic conductor layers formed of copper containing conductor materials, with optimized and enhanced electrical properties.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic fabrications with desirable properties.
Included among the methods, but not limiting among the methods, are methods disclosed within Robinson et al., in U.S. Pat. No. 4,201,579 (a hydrogen plasma stripping method for stripping from a microelectronic fabrication a photoresist layer without oxidizing a microelectronic conductor layer formed within the microelectronic fabrication).
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed in the art of microelectronic fabrication for forming within microelectronic fabrications patterned microelectronic conductor layers with optimized and enhanced electrical properties.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a patterned microelectronic conductor layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the patterned microelectronic conductor layer is formed with optimized and enhanced electrical properties.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, the present invention provides a method for fabricating, with enhanced electrical properties, a microelectronic fabrication having formed therein a patterned microelectronic conductor layer.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a first patterned conductor layer. There is then formed over the first patterned conductor layer a pair of patterned dielectric layers which defines a via which accesses the first patterned conductor layer. There is then treated the pair of patterned dielectric layers and the first patterned conductor layer exposed within the via with at least one of: (1) an argon containing plasma at a radio frequency source power and a radio frequency bias power each less than about 300 watts; and (2) a hydrogen containing plasma at a radio frequency source power of greater than about 400 watts and a radio frequency bias power of greater than about 100 watts, to form from the via a plasma treated via and form from the patterned conductor layer a plasma treated patterned conductor layer.
The present invention provides a method for forming a microelectronic fabrication having formed therein a patterned microelectronic conductor layer, wherein the patterned microelectronic conductor layer is formed with enhanced electrical properties.
The present invention realizes the foregoing objects by plasma treating sidewall and floor components of a via into which is formed the patterned microelectronic conductor layer with at least one of an argon containing plasma and a hydrogen containing plasma, with specific radio frequency source powers and radio frequency bias powers (such at to provide at least one of attenuated electrical leakage, attenuated via resistance thermal instability and attenuated resistance-capacitance delay of the patterned microelectronic conductor layer when formed into the plasma treated via.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of microelectronic fabrication, but employed within the context at least in part of specific process limitations which provide the present invention. Since it is thus at least in part a series of specific process limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 4201579 (1980-05-01), Robinson et al.
patent: 2002/0162736 (2002-11-01), Ngo et al.
Jen Shwangming
Lin Keng-Chu
Pan Shing-Chyang
Gurley Lynne A.
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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