Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-06-29
2001-06-05
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345420, C438S729000
Reexamination Certificate
active
06242360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More specifically, the present invention relates to plasma processing systems which deliver RF power to a plasma processing chamber.
2. Description of the Related Art
Semiconductor processing systems are used to process semiconductor wafers for fabrication of integrated circuits. In particular, plasma-based semiconductor processes are commonly used in etching, oxidation, chemical vapor deposition (CVD), etc. The plasma-based semiconductor processes are typically carried out by means of plasma processing systems and generally include a plasma processing chamber to provide a controlled setting.
FIG. 1
illustrates a schematic block diagram of an exemplary conventional plasma processing system
100
used for processing a semiconductor wafer
102
. The plasma processing system
100
includes a plasma processing chamber
104
, a shield box
106
, a network match box
108
, and an RF generator
110
. The RF generator
110
is coupled to the match network box
108
by a co-axial cable
112
. The shield box
106
is arranged to house or shield a co-axial cable
114
, which couples the match network box
108
to the plasma processing chamber
104
. A helium box
124
, which is mounted on top of shield box
106
, is used for supplying helium to the plasma processing chamber
104
.
The plasma processing chamber
104
includes a shower head
116
and an electrostatic chuck
118
. The shower head
116
is adapted to release a source gas into the chamber
104
for generating plasma over the wafer
102
. The ESC
118
includes one or more dielectric layers
120
disposed over an electrode
122
. The electrostatic chuck
118
functions to hold the wafer
102
in place for processing. The helium from the helium box
124
is provided through a port
140
to control the temperature of the wafer
102
. The plasma processing system
100
also includes an ESC power supply (not shown) for supplying power to the ESC.
Electrostatic chucks are well known in the art and are amply described, for example, in commonly owned U.S. Pat. No. 5,789,904 by Francois Guyot and entitled “High Power Electrostatic Chuck Contact,” U.S. patent application Ser. No. 08/624,988 by Jones et al. and entitled “Dynamic Feedback Electrostatic Wafer Chuck,” U.S. patent application Ser. No. 08/550,510 by Castro et al., and U.S. Pat. No. 5,793,192 by Kubly et al. and entitled “Methods and Apparatus for Clamping and Declamping a Semiconductor Wafer in a Wafer Processing System.” The disclosures of these references are incorporated herein by reference.
For wafer processing, the RF generator
110
provides RF power to the plasma processing chamber
104
. Specifically, the RF generator
110
generates RF power, which is transmitted to the network match box
108
over the co-axial cable
112
. The network match box
108
houses a matching network circuit
126
, which produces an impedance match between the plasma processing chamber
104
and the RF generator
110
during wafer processing. The network match box
108
transmits RF power over the co-axial cable
114
to the plasma processing chamber
104
. The matching network circuit is provided between the RF generator
106
and the plasma processing chamber
104
to minimize reflection of RF power from the plasma processing chamber
104
. It typically includes two or more variable impedance elements (e.g., capacitors, inductors). RF match network circuits are well known in the art and are described, for example, in U.S. patent application No. 5,187,454 by Collins et al. and U.S. patent application Ser. No. 09/218,542 by Arthur M. Howald and filed on Dec. 22 1998. The disclosures of these references are incorporated herein by reference.
In high and medium density plasma etching, semiconductor manufacturers have been using electrical plasma parameters such as the DC bias voltage and the bias peak-to peak voltage to monitor the plasma processing in real time. For example, a DC voltage is typically developed over the wafer
102
and a peak-to-peak voltage can be measured from the electrode
122
during the operation of the plasma processing system
100
. These electrical parameters are often used to diagnose, and if necessary, to interrupt the plasma process to achieve desired plasma processing. These electrical parameters are typically highly sensitive not only to the plasma density and plasma distribution inside the plasma chamber
104
, but also to the spatial distribution of the RF return currents outside the plasma, i.e., through the walls of the plasma chamber
104
, the RF delivery system, and the chassis of the RF matching network.
For example, the plasma processing system
100
of
FIG. 1
delivers forward RF power to the electrode
122
of the ESC
118
via co-axial cable
114
as indicated by arrow
128
. The RF power energizes the electrode
122
, which attracts plasma ions toward the wafer
102
for plasma processing. The walls
130
of the plasma processing chamber
104
provide “return” paths for RF currents to return to the match network box
108
and eventually to the RF generator
110
, thereby forming a closed circuit. Conventional wafer processing systems typically provide as much metal-to-metal surface contact to maximize RF current return paths from the plasma processing chamber
104
to the match network box
108
. For instance, the plasma chamber
104
, shield box
106
, and the match network box
108
are typically formed of a metal (e.g., aluminum) for conducting electricity. Hence, RF currents travel from the walls
130
of the plasma chamber
104
as indicated by arrows
132
over any metal-to-metal contact paths leading to the match network box
108
. Providing as much metal-to-metal contacts for return paths is in accordance with industry standard rule of thumb. For example, designers of plasma processing systems have typically tried to achieve the lowest impedance for RF return current. The lowest impedance is usually achieved by providing as much metal-to-metal contact in the plasma processing systems.
One of the main RF current return paths originates from the walls
130
to the match network box
108
along the coaxial cable
114
as indicated by arrows
134
. In this case, the RF return currents travel along the surface of an outer conductor of the coaxial cable
114
. In addition, RF currents also travel along other return paths over metal-to metal surfaces of the plasma processing chamber
104
, the shield box, and the match network box
108
. In this manner, the plasma processing system
100
is designed to provide as many return paths for RF currents as possible to capture as much stray currents as possible to ensure their return to the match network
126
.
For high wafer yield, it is desirable to maintain consistent and uniform RF return currents in the plasma processing system
100
. Unfortunately, however, providing such metal-to-metal contacts for maximum RF return paths degrades wafer processing over time. For example, the match network box
108
is securely attached to the shield box
106
using a plurality of bolts, screws, etc. through a metal plate (e.g., aluminum plate) disposed between the boxes
108
and
106
. During the life of the plasma processing system
100
, the match network box
108
is often removed from the shield box
106
for routine maintenance or modification. After the maintenance, the match network box is securely re-attached to the shield box by means of an aluminum plate and metal bolts, screws, etc.
The re-attachment of the match network box
108
, however, generally does not precisely duplicate the metal-to-metal contacts existing prior to the removal. For example, the bolts or screws may not be screwed on exactly as before the removal. Thus, the changed metal-to-metal contact characteristics may change the RF current return path characteristics, which in turn lead to changes in the overall magnitude of RF return currents and in the electrical characteristics of the wafer processing. In add
Fischer Andreas
Kadkhodayan Babak
Kuthi Andras
Lam Research Corporation
Martine Penilla & Kim LLP
Powell William
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