Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-12-16
2001-08-21
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345420, C216S059000, C216S067000, C216S075000, C252S079100, C438S009000, C438S742000, C438S740000
Reexamination Certificate
active
06277763
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of Invention
The present invention relates generally to a method and apparatus for dry etching semiconductor wafers. More specifically, the invention relates to a method and apparatus for etching tungsten using a gas mixture comprising a fluorinated gas and oxygen.
2. Background of Prior Art
Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors and resistors on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. Circuit density has a pronounce importance as the speed and number of functions a circuit can execute increases along with the density of the circuit structure. Some design attributes affecting the speed and circuit density of integrated circuits include the resistance and thickness of the materials used to form the layer comprising the circuit structure formed on a substrate.
A material frequently used to fabricate circuit structures is tungsten. Tungsten may be accurately deposited using conventional Chemical Vapor Deposition (CVD) methods and generally has a low resistivity. Circuit designers have found tungsten to be a favorable material for use proximate polysilicon as tungsten exhibits good resistance to permeation by polysilicon, which enables tungsten to retain its physical properties over the course of substrate processing and device use.
In order to maximize circuit density, the layers comprising the circuit structure, including those comprising tungsten, must be minimized. However, when processing such thin layers, care must be taken to avoid damaging the layers during processing. Damaged layers result in defective circuit structures and increased substrate rejects.
One process that can easily damage thin layers is etching. When etching tungsten, the fluorinated chemistry typically employed to remove exposed tungsten on the substrate also is an aggressive etchant of polysilicon. Typical etching systems employ endpoint detection systems that detect the presence of polysilicon in the chamber gases that signal the break through of the tungsten layer and etching of the underlying polysilicon layer. When polysilicon is detected in the exhaust gases, the etch is terminated. Optionally, a timed over-etch step is employed to “clean-up” and remove the residual tungsten that was not removed during the main etch step.
A problem encountered when etching tungsten having an underlying polysilicon layer is the difficulty in controlling the amount of polysilicon etched during the main and optional over-etch of the tungsten. Generally, fluorinated chemistries used for low rate etching, i.e., etch rates of tungsten less than of 2000 Å/min, have poor selectivity to polysilicon. As a result, once the tungsten has been etched to expose the underlying polysilicon layer, the polysilicon is removed at an undesired rate (often substantially equivalent to the etch rate of tungsten). This leads to an unwanted amount of polysilicon being removed before the endpoint can be detected and the etch terminated. For example, over-etching the tungsten layer results in the excessive etching of the underlying polysilicon layer. The resulting trench typically exhibits poor depth control and corner formation.
Although chemistries with higher selectivity are available for tungsten etching, those chemistries generally exhibit high etch rates, i.e., etch rates in excess of 2000 Å/min. Thus, even though polysilicon etches at a slower rate than tungsten, undesirable amounts of polysilicon can be removed prior to end point detection due to the high rate of etch. The result is difficulty in controlling the etch depth. Lack of control of the etch depth is highly undesirable when forming circuit structures from thin layers as the underlying layer may be etched through inadvertently.
Therefore, there is a need in the art for a tungsten etching process having good selectivity to polysilicon.
SUMMARY OF INVENTION
The disadvantages associated with the prior art are overcome by the present invention of a method and apparatus for etching of a substrate comprising both a polysilicon layer and an overlying tungsten layer. The method and apparatus etches the tungsten layer using a plasma formed from a gas mixture comprising a fluorinated gas (for example, CF
4
, NF
3
, SF
6
, and other gases comprising fluorine) and oxygen. The oxygen reacts with the polysilicon that is exposed by the break through of the tungsten layer. The surface oxide, or etch stop layer, that is formed by the oxygen/polysilicon reaction protects the polysilicon from the etchant, thus providing for good selectivity between the polysilicon and tungsten.
REFERENCES:
patent: 4713141 (1987-12-01), Tsang
patent: 4838990 (1989-06-01), Jucha et al.
patent: 5571366 (1996-11-01), Ishii et al.
patent: 0 489 407 A2 (1992-06-01), None
patent: 09082686 (1997-03-01), None
Ootera et al “Highly Selective Etching of W/WN/Poly-Si Gate on Thin Oxide Film with Gaspuff Plasmas” Proceedings of Symposium on Dry Process, pp. 155-160, Nov. 11-12, 1999.
Pan, et al. “Selective Reactive Ion Etching of Tungsten Films in CHF3and Other Fluorinated Gases”, 8257bJournal of Vacuum Science & Technology B, No. 4, pp. 1073-1080, Jul./Aug. 1988.
Theisen, et al. “Maskless Tungsten Etch Process for Plug Fill”, 1046b Extended Abstracts, Spring Meeting, pp. 248-249, May 6-11, 1990.
Kugimiya Katsuhisa
Nishizawa Takanori
Tajima Daisuke
Applied Materials Inc.
Powell William
Thomason Moser & Patterson
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