Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-07
2003-09-09
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S724000
Reexamination Certificate
active
06617255
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a plasma processing method of processing the surface of semiconductor devices, and more particularly to such a plasma processing method suitable for etching of a silicon nitride film.
A method using plasma is widely employed to work or process semiconductor devices. In the prior art, as the plasma used to etch a silicon nitride layer, plasma of a mixed gas of fluorine-containing gas as a main component with hydrogen-containing gas and oxygen-containing gas is utilized as disclosed in U.S. Pat. No. 5,756,402.
SUMMARY OF THE INVENTION
In recent years, with the high integration of semiconductor devices, miniaturization or fine patterning thereof is required. For this purpose, the accuracy of size for etching a lightly doped drain (hereinafter abbreviated to LDD) spacer influencing a length of a gate channel of a metal oxide semiconductor (MOS) is important. Further, recently, with the high integration of semiconductor devices, a method of forming the LDD spacer of a silicon nitride layer is used in order to apply the self-alignment contact (SAC) technique thereto. Accordingly, the etching technique of the LDD spacer requires the high accuracy of size in the anisotropy and the high selectivity to the silicon oxide layer constituting the underlayer.
FIG. 8
shows a cross section of a sample fabricated by etching the silicon nitride layer using fluorine-containing gas as a main component in the prior art. In the initial state of the fabrication of the sample, as shown in
FIG. 1A
, after a gate oxide layer
102
made of a silicon oxide, a gate electrode
104
made of a polycrystal silicon, a mask
106
for the gate electrode
104
and a gate covering insulation layer
103
made of a silicon oxide have been formed, a silicon nitride layer
105
is formed thereon. When fluorine-containing gas is used as etching gas, a rate selectivity (selectivity) of the silicon nitride layer to the silicon oxide layer can be made larger, the isotropy is strengthened and the side etching is produced in the silicon nitride layer
105
as shown in FIG.
8
. In addition, the silicon nitride layer on the side of the gate electrode
104
is narrowed and the processing accuracy in size is deteriorated.
It is an object of the present invention to solve the above problems by providing a plasma processing method capable of increasing a selectivity of a silicon nitride layer to a silicon oxide layer constituting the underlayer and improving the processing accuracy in size of the silicon nitride layer.
In order to solve the above problem, according to an aspect of the present invention, the silicon nitride layer is etched using halogen such as chlorine gas containing no fluorine to thereby prevent isotropic etching of the silicon nitride layer and a semiconductor device is processed by means of plasma mixed with aluminum in order to suppress the etching rate of the silicon oxide layer.
Other objects, features and advantages of the present invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6136211 (2000-10-01), Qian et al.
patent: 6146954 (2000-11-01), Klein et al.
patent: 6180533 (2001-01-01), Jain et al.
patent: 6235643 (2001-05-01), Mui et al.
patent: 6287974 (2001-09-01), Miller
Arase Takao
Ishimura Hiroaki
Saito Go
Sakaguchi Masamichi
Shimomura Takahiro
Antonelli Terry Stout & Kraus LLP
Deo Duy-Vu
Utech Benjamin L.
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