Plasma process for selectively etching oxide using...

Details Plasma process for selectively etching oxide using... Plasma process for selectively etching oxide using...

1999-03-01

2002-03-26

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Forming groove or hole in a substrate which is subsequently...

C216S067000, C216S072000, C216S079000, C216S080000, C438S719000, C438S723000, C438S738000, C438S743000, C438S744000

Reexamination Certificate

active

06361705

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to etching in semiconductor processing. In particular, the invention relates to plasma etching of silicon oxide layers, preferably in a process producing high selectivity to silicon nitride or other non-oxide materials and not etch stop and exhibiting a wide process window.
BACKGROUND ART
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors, or other electronic devices that can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes. Furthermore, advanced processes are being used which are much more tolerant to minute inaccuracies during processing. However, these processes often make extraordinary demands upon the chemistry of the etching process. Oxide etching has presented some of the most difficult demands. Oxide etching refers to the etching of layers of silicon dioxide, silica glass such as BPSG, and related oxide materials that serve as electrical insulators. Advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective oxide layers. Small contact or via holes need to be etched through each of the oxide layers.
An example of an advanced oxide etching process is a self-aligned contact (SAC) process. An example of a SAC structure for two MOS transistors is illustrated in the cross-sectional view of FIG.
1
. Two polysilicon lines
10
,
12
are deposited and defined over a silicon substrate
14
. Each polysilicon line
10
,
12
forms a gate structure intended to operate as a gate electrode for a respective MOS transistor. The polysilicon lines
10
,
12
act as a mask for the ion implantation of a p-type or n-type dopant into a source region
16
for both of the MOS transistors. Unillustrated drain regions are also formed to complete the principal portions of the MOS transistors.
An LPCVD process is used to coat a thin conformal layer
18
of silicon nitride (Si
3
N
4
) on the exposed silicon substrate
14
and on the polysilicon lines
10
,
12
. A narrow portion
20
of the silicon nitride layer
22
is formed over the silicon substrate
14
in a gap
22
between the nitride-covered gate structures
10
,
12
. This narrow portion
20
is removed by a post nitride etch following the oxide etch to expose the underlying silicon
14
for contacting. The gap
22
is made as small as possible consistent with subsequent processing in order to increase the integration level.
An oxide layer
24
is then deposited, usually by plasma-enhanced chemical vapor deposition (PECVD), to act as an interlevel dielectric. Considerations of dielectric breakdown with normal operating voltages limit the minimum thickness of the oxide layer
24
to between 0.5 &mgr;m and 1 &mgr;m. A photolithographic step including depositing and photographically defining a photoresist mask
25
followed by an oxide etch forms a contact hole
26
extending to the narrow silicon nitride portion
20
above the silicon source region
16
. Following the post nitride etch to remove the narrow silicon nitride portion
20
, the contact hole
26
is filled with aluminum or other conductor to form a plug electrically connecting the source region
16
of the two MOS transistors to the wiring level above the dielectric layer
24
. The silicon nitride layer
18
acts as an electrical insulator relative to the aluminum plug to isolate the plug from the polysilicon lines
10
,
12
.
The SAC oxide etch process must satisfy several difficult requirements. The contact hole
26
should be as narrow as possible to increase the integration level, but the oxide thickness is relatively fixed at a significantly larger length. As a result, the contact hole
26
has a high aspect ratio of depth to width. A high aspect ratio can be accomplished only with a highly anisotropic etch, with the wall slope being greater than, for example, 85° and preferably close to 90°.
In view of the large number of structures on a wafer and the variations in oxide thickness, it is highly desirable that the oxide etch be highly selective to silicon nitride, that is, that the etch process etch oxide
24
much more quickly than the underlying silicon nitride
18
. The contact hole
26
can then be over etched, for example by 100% of the design depth, to accommodate non-uniformities or process variations, thus assuring that the contact hole reaches the bottom nitride portion
20
over the silicon source region
16
. But if the etching manifests high selectivity, there is little etching of the silicon nitride so the source region
16
can be made relatively thin.
If the gap
22
is made very small, various considerations may limit the width of the contact hole
26
to be greater than the size of the gap
22
. Also, there may be some uncontrolled variations in the position of the contact hole
26
. With a nitride selective etch, the contact hole
26
can overlap the polysilicon lines
10
,
12
, and small variations of the location of the contact hole
26
can be accommodated while contact to the silicon is still assured. A SAC etch is usually also selective to silicon.
As illustrated, the width of the contact hole
26
is about the same as that of the gap
22
between the nitride-covered polysilicon lines
10
,
12
, but the photolithographic variations cause the contact hole
26
to be offset from the gap
22
and to expose a corner
27
of the nitride layer
18
. Alternatively, the width of the contact hole
26
may be made significantly larger than the width of the gap
22
so that two nitride corners
27
are exposed. Since the nitride corners
27
are exposed the longest to the oxide etch and the acute corner geometry favors etching, nitride corner loss is often the most critical selectivity issue in contact or via etching. The etch process is subject to other constraints, such as the selectivity to the patterned photoresist overlying the oxide layer
24
. The photoresist is prone to form facets
28
. If the facets extend to the underlying oxide
24
, the resolution of the photolithography is degraded. However, nitride corner loss is generally considered to be the most demanding selectivity requirement in a SAC process.
Another difficult oxide etch technique not necessarily involving nitrides is a bi-level contact. A single etch is used to simultaneously etch through an upper oxide inter-level layer to a thin polysilicon line underlying the upper oxide layer and also etch through both the upper and a lower oxide inter-level layer to another polysilicon line underlying the lower oxide layer. This technique requires very high selectivity to silicon to avoid etching through the upper polysilicon line while the lower oxide layer is being etched through.
It is now known that reasonably good oxide etch processes can be achieved by using a fluorocarbon or hydrofluorocarbon etching gas, such as the respective types CF
4
or CHF
3
or higher-order compounds of the two types. These two types of etchants may be referred to as a hydrogen-free fluorocarbon and a hydrofluorocarbon although the common terminology includes both hydrogen-free fluorocarbons and hydrofluorocarbons as fluorocarbons. Fluorocarbons formed in linear chains are referred to as fluoroalkanes, using standard organic chemistry nomenclature. Under the proper conditions, the fluorocarbon forms a low-fluorine polymer on the silicon and the nitride but not on the oxide. Thereby, the oxide is etched but the silicon and nitride are not. However, if the fluorine content of the etching gas is too high, the fluorine can etch the underlying silicon or nitride and the selectivity is lost. It is believed that CF
x
radicals selectively etch oxide over silicon or nitride, but F radicals etch silicon and nitride as well.
The polymer introduces a further problem of etch stop. In narrow deep holes being etched, that is, holes of high aspect ratio, excess polymer is formed over the oxide walls and floor, and etching

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