Plasma immersion ion implantation process

Details Plasma immersion ion implantation process Plasma immersion ion implantation process

1996-08-19

2003-10-14

Padgett, Marianne (Department: 1762)

Coating processes

Direct application of electrical, magnetic, wave, or...

Ion plating or implantation

C427S527000, C427S530000, C427S535000, C427S569000, C118S7230ER

Reexamination Certificate

active

06632482

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to process for doping of semiconductor materials by ion implantation with particular application to shallow junction devices.
BACKGROUND OF THE INVENTION
Modern electronic devices are based on semiconductor materials. A semiconductor has a crystalline structure in which very few electrons are mobile so that the intrinsic conductivity is too low to be useful as an electronic device. It is known to add small amounts of certain types of impurity to the crystal lattice to provide current carriers. The process of adding those impurities is known as “doping”. The earliest technique for doping was accomplished by surrounding a semiconductor wafer with a gas comprising the dopants to be implanted and raising the temperature high enough to permit diffusion of the impurity atom into the lattice structure.
As the demand increased for more precise control over spatial uniformity and concentration of dopants, a device known as an ion implanter became the usual tool for adding the necessary impurity to a crystal. These implanters are large complex devices having very precise control of a dopant ion beam energy, position and scan rate. Very recently, for shallow junction formation, it has been recognized that the raster scan ion implanter has limitations at low energy beam conditions, under 10 KV, especially where dose and production rate, i.e. wafer throughput, requirements are high. Another method known as PI
3
(Plasma Immersion Ion Implantation) is being studied because the dose rate is high at lower energy and the equipment is inexpensive. Prior PI
3
methods employed a continuous plasma in the vacuum chamber.
In an earlier filed application, Ser. No. 844,353, dated Mar. 3, 1992, assigned to the same assignee, in which this inventor is a co-inventor, the PI
3
concept is improved by use of variable duty cycle ion accelerating pulses in conjunction with a cylindrical target mounted on a plasma chamber wall. Although this earlier application was an improvement in shallow junction, low energy high current implantation, there are several problems with that approach. Even when the electrode behind the wafer was essentially completely shielded from ion bombardment, unintended impurities due to plasma etching were present in the chamber and were being implanted. Also, large particles were being formed in the plasma and on the wafer surface.
The object of this invention is to overcome the prior art PI
3
contamination and particle problem and at the same time enable high yield manufacturing of shallow junction implantations without breakdown of any thin dielectric.
A secondary object is to provide inexpensive, high throughput apparatus for PI
3
of a semiconductor, having adequate uniformity and implant dose control.
SUMMARY OF THE INVENTION
A method of accomplishing PI
3
using a pair of power supplies and very short ionization negative pulses applied to the primary cathode underlying the wafer in conjunction or followed by short ionization pulses applied to a second cathode which is facing toward the primary (wafer) electrode to provide neutralizing electrons.
The on-time and the duty cycle of the primary cathode ionization pulses are made to be short enough so that no particles can grow in the BF
3
plasma. The neutralizing electrons necessary to protect the dielectric are provided by the secondary cathode.


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