Plasma etching methods

Details Plasma etching methods Plasma etching methods

1999-09-15

2001-07-10

Mills, Gregory (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C134S001100, C134S001200, C134S022100, C438S711000, C438S734000

Reexamination Certificate

active

06258728

ABSTRACT:

TECHNICAL FIELD
This invention relates to plasma etching methods.
BACKGROUND OF THE INVENTION
Plasma etchers are commonly used in semiconductor wafer processing for fabrication of contact openings through insulating layers. A photoresist layer having contact opening patterns formed therethrough is typically formed over an insulative oxide layer, such as SiO
2
and doped SiO
2
. An oxide etching gas, for example CF
4
, is provided within the etcher and a plasma generated therefrom over the wafer or wafers being processed. The etching gas chemistry in combination with the plasma is ideally chosen to be highly selective to etch the insulating material through the photoresist openings in a highly anisotropic manner without appreciably etching the photoresist itself. A greater degree of anisotropy is typically obtained with such dry plasma etchings of contact openings than would otherwise occur with wet etching techniques.
One type of plasma etcher includes inductively coupled etching reactors. Such typically include an inductive plasma generating source coiled about or at the top of the reactor chamber and an electrostatic chuck within the chamber atop which one or more wafers being processed lies. The electrostatic chuck can be selectively biased as determined by the operator. Unfortunately when utilizing etching components having both carbon and fluorine, particularly in inductively coupled etching reactors, a polymer develops over much of the internal reactor sidewall surfaces. This polymer is electrically insulative and continually grows in thickness during the wafer etching process. In addition, the polymer can react with species in the plasma and cause process results to vary as the polymer thickness changes. For an etch 2 microns deep on the wafer, the polymer thickness on certain internal reactor surfaces can be 3000 Angstroms to 6000 Angstroms. It is highly desirable to remove this polymer because it can make process results vary and can contribute to particle contamination of the wafer(s) being processed.
The typical prior art process for cleaning this polymer material from the reactor employs a plasma etch utilizing O
2
as the etching gas. It is desirable that this clean occur at the conclusion of etching of the wafer while the wafer or wafers remain in situ within the reactor chamber. This both protects the electrostatic chuck (which is sensitive to particulate contamination) during the clean etch, and also maximizes throughput of the wafers being processed. An added benefit is obtained in that the oxygen plasma generated during the clean also has the effect of stripping the photoresist from over the previously etched wafer.
One prior art plasma clean is conducted in three steps when using a LAM 9100 type inductively coupled plasma etcher. In a first plasma cleaning step, top electrode power is provided at 600 Watts and the bottom at 200 Watts. O
2
feed is provided at 750 sccm for 15 seconds, with pressure being maintained at 15 mTorr. In the second step, top power is at 1750 Watts, the bottom electrode is not biased (0 Watts), and O
2
feed is provided at 500 sccm for 20 seconds with pressure being maintained at 80 mTorr. In a third step, the pins of the electrostatic chuck are raised to lift the wafer(s), and the top power is provided at 1200 Watts, the bottom electrode is not biased (0 Watts), and O
2
feed is provided at 500 sccm for 15 seconds with pressure being maintained at 80 mTorr.
However in the process of doing reactor clean etches, there is an approximate 0.025 micron or greater loss in the lateral direction of the contact. In other words, the contact openings within the insulating layer are effectively widened from the opening dimensions as initially formed. This results in an inherent increase in the critical dimension of the circuitry design. As contact openings become smaller, it is not expected that the photolithography processing will be able to adjust in further increments of size to compensate for this critical dimension loss.
Accordingly, it would be desirable to develop plasma etching methods which can be used to minimize critical dimension loss of contact openings, and/or achieve suitable reactor cleaning to remove the polymer from the internal surfaces of the etching chamber. Although the invention was motivated from this perspective, the artisan will appreciate other possible uses, with the invention only be limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.
SUMMARY OF THE INVENTION
In but one aspect of the invention, a plasma etching method includes forming polymer material over at least some internal surfaces of a dual powered plasma etch chamber (for example a high density oxide etcher, where “high density” refers to a plasma density of at least 10
10
ions/cm
3
) while first plasma etching an outer surface of a semiconductor wafer received by a wafer holder within the chamber. After the first plasma etching, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder effective to produce an ac peak voltage at the wafer surface of greater than zero and less than 200 Volts. In one implementation, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder of greater than zero Watts and less or equal to about 1 Watt/cm
2
of wafer surface area on one side. In one implementation, second plasma etching is conducted of polymer material from the chamber internal surfaces with the wafer in the chamber while providing a bias power ratio of top to bottom power of at least about 10:1. In one implementation, plasma etching is conducted of polymer material from the chamber internal surfaces under conditions producing a greater etch rate of wafer outermost surfaces than an etch rate of the feature sidewall surfaces. In one implementation, plasma etching is conducted of polymer material from the chamber internal surfaces under conditions which also etch wafer outermost surfaces selectively relative to the feature sidewall surfaces. Other aspects and implementations are contemplated.


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Product Bulletin, “TCP™ 9100 High-Density Oxide Etch System Productivity Solution For Advanced Oxide Etch”, LAM Research Corporation, Fremont, CA 9 pages (undated).

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