Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-10-02
2003-05-27
Goudreau, G (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S723000, C438S724000, C438S734000, C438S694000, C438S692000, C438S704000, C134S001200
Reexamination Certificate
active
06569777
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to multi-layered semiconductor structures and more particularly to a method for forming a dual damascene structure with improved an improved via profile to improve electrical performance including electromigration resistance and improved metal filling characteristics.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer interconnects and intra-layer interconnects have increasingly high aspect ratios (e.g., an interconnect opening depth to diameter ratio of greater than about 4). In particular, high aspect ratio vias require uniform etching profiles including preventing formation of unetched residues around the via openings during anisotropic etching of an overlying trench structure in a dual damascene formation process. Such residual oxides, also referred to as via fences, detrimentally affect subsequent processes including adhesion/barrier layer deposition and metal filling deposition frequently resulting in degraded device performance including electrical pathway open circuits.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision of a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intra-layer conductive interconnects and inter-layer conductive interconnects formed by anisotropically etched openings in an dielectric insulating layer, often referred to as an inter-metal dielectric (IMD) layer, which are subsequently filled with metal. Commonly used inter-layer high aspect ratio openings are commonly referred to as vias, for example, when the opening extends through an insulating layer between two conductive layers. The intra-layer interconnects extending horizontally in the IMD layer to interconnect different areas within an IMD layer are often referred to as trench lines. In one manufacturing approach, trench lines are formed overlying and encompassing one or more vias to form metal inlaid interconnects referred to as dual damascene structures.
In a typical process for forming multiple layer interconnect structure, for example, a dual damascene process, via openings are first anisotropically etched through an IMD layer by conventional photolithographic and etching techniques. A second anisotropically etched opening referred to as a trench line is then formed according to a second photolithographic patterning process overlying and encompassing one or more of the via openings. The via openings and the trench line together makeup the dual damascene structure which is subsequently filled with metal, for example, copper, followed by a CMP planarization process to planarize the wafer process surface and prepare the process surface for formation of another overlying layer or level in a multi-layered semiconductor device.
One approach to increasing signal transport speeds has been to reduce the dielectric constant of the dielectric insulating material used to form IMD layers thereby reducing the capacitance contribution of the IMD layer. Typical low-k (low dielectric constant) materials in use have included carbon doped silicon dioxide and other materials which tend to form a porous material thereby reducing the overall dielectric constant. Porous low-k materials have several drawbacks including enhanced absorption of chemical species by which may easily migrate throughout the IMD layer.
As feature sizes in anisotropic etching process have diminished, photolithographic patterning processes require activating light (radiation) of increasingly smaller wavelength. For 0.25 micron and below CMOS technology, deep ultraviolet (DUV) photoresists have become necessary to achieve the desired resolution. Typically DUV photoresists are activated with activating light source wavelengths of less than about 250 nm, for example, commonly used wavelengths include 193 nm and 248 nm. Many DUV photoresists are chemically amplified using a photoacid generator activated by the light source to make an exposed area soluble in the development process.
One problem affecting the anisotropic etching of dual damascene features, particularly with respect to the trench portion etching process has been thought in the prior art to be related to the use of DUV photoresist processes to pattern the trench portion for etching. For example, photoresist residue also referred to as scum frequently forms on the sidewalls of the via prior to the trench etching process and has been believed to degrade subsequent etching profiles of the completed dual damascene structure. The photoresist residue has been attributed to interference of residual nitrogen-containing species, for example amines, with the DUV photoresist. Residual nitrogen-containing species contamination have been thought to originate from amine containing CVD precursors which are frequently used to deposit nitride etching stop layers and anti-reflectance coating (ARC) layers. Nitrogen containing species are known to interfere with chemically amplified DUV photoresists by neutralizing a photogenerated acid catalyst which thereby renders the contaminated portion of the photoresist insoluble in the developer. Regardless of the precise cause of such photoresist residue, the residue frequently remains on patterned feature edges, sidewalls, or floors of features, detrimentally affecting subsequent anisotropic etching profiles. During anisotropic etching of an overlying feature, for example a trench line opening overlying a via opening, residual photoresist for a trench line patterning step remains on via opening sidewalls. Consequently, during etching of the trench opening upon reaching the via level, uneven etching occurs around the via opening area causing, for example, a via fence of etching resistant material to form around the via opening. Such undesirable etching profiles detrimentally affect subsequent metal filling processes adversely affecting adhesion of overlayers of material and detrimentally affecting electrical performance and device reliability.
There is therefore a need in the semiconductor processing art to develop a method to reliably anisotropically etch dual damascene structures to avoid forming via fences to achieve improved device reliability and electrical performance.
It is therefore an object of the invention to provide a method to reliably anisotropically etch dual damascene structures to avoid forming via fences to achieve improved device reliability and electrical performance while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for plasma etching a semiconductor feature to improve an etching profile.
In a first embodiment, the method includes providing a semiconductor wafer comprising a first feature opening anisotropically etched though a thickness portion of at least one dielectric insulating layer; anisotropically etching a second feature opening overlying and at least partially encompassing the first feature opening according to a reactive ion etch (RIE) process to leave an unetched portion surrounding a first feature opening portion at about a bottom portion level of the second feature opening; and, plasma treating the first and second openings with a plasma formed of a mixture of oxygen and nitrogen plasma source gases including an applying an independently variable RF bias power source to the semiconductor wafer to remove the unetched portion.
These and other embodiments, aspects and features of the invention will become better understood
Chang Feng-Yueh
Hsin Pin-Yi
Hsu Jyh-Shiou
Goudreau G
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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