Etching a substrate: processes – Etching and coating occur in the same processing chamber
Reexamination Certificate
1999-11-18
2004-09-14
Goudreau, George A. (Department: 1763)
Etching a substrate: processes
Etching and coating occur in the same processing chamber
C216S079000, C438S719000, C134S001100, C134S001200, C134S021000
Reexamination Certificate
active
06790374
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming etched silicon layers within microelectronic fabrications. More particularly, the present invention relates to plasma etch methods for forming with attenuated plasma etch residue plasma etched silicon layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become more common in the art of microelectronic fabrication to employ plasma etch methods for forming etched silicon layers, including but not limited to etched monocrystalline silicon layers, etched polycrystalline silicon layers and etched amorphous silicon layers, within microelectronic fabrications.
Such plasma etch methods often employ plasma etchant gas compositions which upon plasma activation provide active bromine and/or chlorine containing etchant species, such as may be derived, for example and without limitation, from etchant gases including but not limited to bromine, hydrogen bromide, chlorine and/or hydrogen chloride. Similarly, such etched silicon layers formed within microelectronic fabrications may include, but are not limited to: (1) partially etched monocrystalline silicon semiconductor substrate layers having shallow and/or deep isolation and/or capacitive trenches etched therein as employed within semiconductor integrated circuit microelectronic fabrications, as well as; (2) fully etched and patterned polycrystalline silicon non-substrate layers which may be employed as: (a) patterned polysilicon conductor layers within microelectronic fabrications including but not limited to semiconductor integrated circuit microelectronic fabrications, as well as; (b) gate electrodes within field effect transistors (FETs) employed within semiconductor integrated circuit microelectronic fabrications.
Similarly, such etched silicon layers when formed within microelectronic fabrications while employing plasma etch methods which employ etchant gas compositions which upon plasma activation provide active bromine and/or chlorine containing etchant species are often formed in the presence of silicon containing dielectric layers, such as but not limited to silicon oxide dielectric layers, silicon nitride dielectric layers and silicon oxynitride dielectric layers. The silicon containing dielectric layers may be formed as plasma etch mask hard mask patterned silicon containing dielectric layers, or in the alternative as substrate layers, such as, for example and without limitation, as gate dielectric silicon containing dielectric layers formed beneath gate electrodes formed within field effect transistors (FETs) employed within semiconductor integrated circuit microelectronic fabrications.
While plasma etch methods for forming etched silicon layers for use within microelectronic fabrications are thus desirable and common within the art of microelectronic fabrication, plasma etch methods for forming etched silicon layers for use within microelectronic fabrications are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is known in the art of microelectronic fabrication that: (1) it is often difficult to reproducibly and controllably form while employing plasma etch methods etched silicon layers with attenuated residue formation (such as but not limited to attenuated particulate contamination residue formation) within microelectronic fabrications; and (2) in situations where the etched silicon layers are formed in the presence of silicon containing dielectric layers, it is often difficult to reproducibly and controllably form the etched silicon layers with enhanced selectivity of the plasma etch methods for the etched silicon layers with respect to the silicon containing dielectric layers.
It is thus towards the goal of providing for use when fabricating microelectronic fabrications plasma etch methods for reproducibly and controllably forming within microelectronic fabrications etched silicon layers with: (1) attenuated residue formation (such as but not limited to particulate contamination residue formation); and (2) enhanced selectivity of the plasma etch methods for the etched silicon layers with respect to silicon containing dielectric layers when those etched silicon layers are formed in the presence of silicon containing dielectric layers, that the present invention is directed.
Various plasma processing methods have been disclosed in the art of microelectronic fabrication for forming plasma processed microelectronic layers with desirable properties within microelectronic fabrications.
For example, Gupta et al., in U.S. Pat. No. 5,456,796, discloses a plasma processing method for attenuating particulate generation and deposition upon a substrate employed within a microelectronic fabrication when processing the substrate employed within the microelectronic fabrication while employing the plasma processing method. The plasma processing method employs: (1) a rapid increase of a plasma power within a plasma reactor chamber to a high plasma power level prior to introduction of the substrate into a plasma reactor chamber to thus provide for effective cleaning of the plasma reactor chamber prior to introduction of the substrate into the plasma reactor chamber, in conjunction with; (2) a slower increase of the plasma power within the plasma reactor chamber subsequent to introduction of the substrate into the plasma reactor chamber in order to avoid circulation of particles within the plasma reactor chamber which would otherwise settle upon the substrate.
In addition, Saito et al., in U.S. Pat. No. 5,681,424, disclose a plasma processing method for cleaning a plasma reactor chamber within which is plasma etched a silicon layer formed over a substrate while employing a hydrogen bromide containing etchant gas composition, while simultaneously dissipating an electrostatic charge formed upon the substrate incident to use within a plasma apparatus employed within the plasma processing method of an electrostatic chuck for securing the substrate within the plasma reactor chamber. The plasma processing method employs an oxygen containing etchant gas composition for simultaneously cleaning the reactor chamber and dissipating the electrostatic charge formed upon the substrate.
Further, Leung et al., in U.S. Pat. No. 5,705,080, disclose a plasma processing method for cleaning deposits from within a reactor chamber, including but not limited to a plasma reactor chamber, without damaging within the reactor chamber reactor components which are otherwise sensitive to the plasma processing method. The plasma processing method employs covering within the reactor chamber components which are otherwise sensitive to the plasma processing method prior to cleaning the deposits from within the reactor chamber while employing the plasma processing method.
Still further, Murugesh et al., in U.S. Pat. No. 5,811,356, disclose a plasma processing method and a plasma processing apparatus which provide for a reduced concentration of mobile ions and metal contaminants within a reactor chamber so that there may be fabricated within the reactor chamber microelectronic layers, particularly microelectronic dielectric layers, with enhanced reliability. The method employs, when seasoning the reactor chamber while employing the plasma processing method and the plasma processing apparatus, a bias radio frequency power density of greater than 0.051 watts per square millimeter and a seasoning time of greater than about 30 seconds.
Finally, Gupta, in U.S. Pat. No. 5,824,375, discloses a plasma processing method and a plasma processing apparatus for reducing fluorine and other sorbable contaminants in a plasma reactor chamb
Dai Xuechun
Ho Kwok Keung Paul
Chartered Semiconductor Manufacturing Ltd.
Goudreau George A.
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
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