Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1994-05-09
1997-05-13
Breneman, R. Bruce
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
156345, 216 71, 118723E, 427569, 438729, 438763, 438778, 438697, C23F 102
Patent
active
056288697
ABSTRACT:
A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer. A method, and apparatus for practicing the method, are set forth along with an explanation of how particular geometric factors of electrodes used in the PECVD process affect the resulting thickness non-uniformities. The thickness non-uniformities of the sub-layers may also be largely abated by use of the invention in a predictive-corrective fashion. A similar predictive-corrective method and resulting apparatus is set forth for gas plasma etching of an existing layer of material on a semiconductor integrated circuit processing wafer.
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Alanko Anita
Breneman R. Bruce
LSI Logic Corporation
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